hi RJH,
I got furhter enquires from customer:
With regards to the figures 110-129:
- We assume that LO output buffer and LO div blocks are activated. Is that correct?
- An abrupt power dissipation (for +3.3V pwr supply) increase is depicted at figures 110-115 at frequencies approx 3GHz. However as noted in the data sheet , a constant Txdiv=1, Lo div=1 setup should be used for Fout=2050Mà 4100M. Please clarify.
- figures 111, 113 depict “ +3.3V supply current vs supply, High gain mode”, with graphs labels “+3.3V, 5V”.
To which power supply rail the “5V” refers to?
Does the total Icc_3.3V depends on any other power supply rail Icc (ex. Vcc_tk)?
- figure 115 depicts “ 5V supply current vs supply, low power mode”. However as specified in the data sheet the typ Icc_Tk=21mA and not >200mA as the graph depicts.
- Figures 119,121,123 depict “ 3.3V Pdiss vs supply” with labels “+3.3V, 5V”.
To which power supply rail the “5V” refers to?
thansk a lot in advance
KR
Vincenzo