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DAC38RF82: Pin J5 and sync signal

Part Number: DAC38RF82

Hello,

We are now debugging DAC38RF82 in the mode LMFSHD=82121, we facing some problems need your help:

1. When we power up DAC38RF82, the sync signal (pin number C4) started in a logic high state. There is no process from low to high when we established the connection between the FPGA and DAC38RF82. The DAC38rf82 is no output.The sync signal state is different from the other products what I have used(adi ad9144). can you give me some suggestions?

2. The datasheet recommend the pin J5 should be connected to ground if not used. But we make a mistake when we design circuits, this pin is left floating. Is there any influence on other functions if we ignore the mistake?

Regards,

tang

  • Tang,

    For #1, please follow the steps shown in section 9.1.1, Start-up Sequence. There are several steps involved to get the SYNC to toggle.

    For #2,  TRST has an internal pull-up, so if you are floating this signal, the DAC will see this as a logic "1", which may force the part into JTAG test mode. I will look into this more.

    Regards,

    Jim

  • Hi Jim,

    I really appreciate your support . If you have any other findings of the pin J5, please tell me.

    I need your help with another problem. I want to know how to configure the SerDes PLL? I use the model 84111, 2TX, 8X, JESD lane rate 11.25Gbps, DAC PLL output 9G.

    The relationship as follow:

    DAC PLL output 9G / 4 / SERDES_REFCLK_DIV (4) = SERDES PLL REFCLK(562.5MHz)

    SERDES PLL REFCLK(562.5MHz) x MPY(0x43C,5) = SERDES PLL OUTPUT (2.8125GHz)= 0.25 x JESD LANE RATE (11.25Gbps)

    8MHz < SERDES PLL REFCLK / BWSCALE(Low loop bandwidth 21 ) < 30MHz

    Is this correct?

    So the SerDes PLL register configuration :

    Address      Data

    0x43B          0x9800

    0x43C          0x9051

    0x43D          0x0088

    0x43E          0x0909

    0x43F          0x0000

    The SerDes PLL goes out of lock and the register( 0x05[2:1] ) is always "11".

    I also find that the multiply factor MPY is different between datasheet( in table 4 of Page 27) and the software DAC38RF8x EVM GUI V3P0

    Thanks,

    Tang

  • Tang,

    The values should be as follows:

    Address      Data

    0x43B          0x9802

    0x43C          0x8029

    0x43D          0x0088

    0x43E          0x0929

    0x43F          0x0000

    What frequency is your DAC PLL reference clock?

    Regards,

    Jim

  • Jim,

     DAC PLL reference clock  is 562.5MHz. The M parameter is set to 4 and the N parameter is set to 1. Does this have any impact on SerDes PLL?

    Regards,

    Tang

  • Hi Jim,

    I have used the SerDes PLL registers configuration that you have provided, but the SerDes PLL is still unlocked. Do you have any other suggestions for solving the problems? Are there any other registers that may have an impact on SerDes PLL?

    What frequency is your SYSREF clock when using the model 84111?

    Thanks,

    Tang

  • Tang,

    SYSREF is data rate / K * N. Sample rate is 9G/8 = 1125MHz. If K = 20 and we use a value of 4 for N, SYSREF = 14.0625MHz. N can be any whole integer.

    Regards,

    Jim