I have attached ultra wideband mode configuration file of GC4016. This configuration is working fine for Decimations 8,10 and 16 and not working for 9,11,12,13,14 and 15. Why it is behaving like that.
/* Wideband configuration file */
/* general modes register */
global_reset 1
out_blk_reset 1
pad_reset 1
resampler_reset 1
edge_write 1
ck_2x_en 0
ck_2x_test 0
ck_loss_detect 0
/* general sync */
lvds 0
4_bit_address 0
output_sync 4
diag_sync 7
/* count sync */
one_shot 1
os_mode 1
count_test 0
counter_sync 7
diag_source 0
/* terminal count */
cnt 0
/* channel configurations */
channel 0
phase 0
freq 0x4CCCCCCD
cfir_coef ../Taps/cfir_150.taps
pfir_coef ../Taps/pfir_150.taps
ch_reset 0
use_shift 1
shift 4
freq_sync 7
phase_sync 7
dither_sync 0 /* Original is 4 */
nco_sync 4
zpad_en 0
zpad_sync 4
nzeros 0
flush_sync 4
dec_sync 4
dec 7
gain_sync 7
mix20b 1
big_scale 7
scale 5 /* Changed - ELSEC */
qonly 0
ionly 1
splitiq 1
neg_ctl 0
test 0
coarse 0
idly_cfir 0
qdly_cfir 0
no_sym_cfir 0
peak_select 0
idly_pfir 0 /* Changed - ELSEC */
qdly_pfir 1
no_sym_pfir 0
msb_pol 0
in_fmt 0
ab_sel 0
input_sel 0
peak_mode 0
peak_threshold 3
peak_sync 5
fine_gain 1070
channel 1
/* copy_channel 0 same as 0 */
/* ch_reset 1*/
phase 0x4000
freq 0x4CCCCCCD
cfir_coef ../Taps/cfir_150.taps
pfir_coef ../Taps/pfir_150.taps
ch_reset 0
use_shift 1
shift 4
freq_sync 7
phase_sync 7
dither_sync 0 /* Original is 4*/
nco_sync 4
zpad_en 0
zpad_sync 4
nzeros 0
flush_sync 4
dec_sync 4
dec 7
gain_sync 7
mix20b 1
big_scale 7
scale 5 /* Changed - ELSEC */
qonly 1
ionly 0
splitiq 1
neg_ctl 0
test 0
coarse 0
idly_cfir 0
qdly_cfir 0
no_sym_cfir 0
peak_select 0
idly_pfir 0 /* Changed - ELSEC */
qdly_pfir 1
no_sym_pfir 0
msb_pol 0
in_fmt 0
ab_sel 0
input_sel 0
peak_mode 0
peak_threshold 3
peak_sync 5
fine_gain 1070
channel 2
/* copy_channel 0 same as 0 */
/* ch_reset 1*/
phase 0x0
freq 0x4CCCCCCD
cfir_coef ../Taps/cfir_150.taps
pfir_coef ../Taps/pfir_150.taps
ch_reset 0
use_shift 1
shift 4
freq_sync 7
phase_sync 7
dither_sync 0 /* Original is 4*/
nco_sync 4
zpad_en 0
zpad_sync 4
nzeros 0
flush_sync 4
dec_sync 4
dec 7
gain_sync 7
mix20b 1
big_scale 7
scale 5 /* Changed - ELSEC */
qonly 0
ionly 1
splitiq 1
neg_ctl 0
test 0
coarse 0
idly_cfir 0
qdly_cfir 0
no_sym_cfir 0
peak_select 0
idly_pfir 0
qdly_pfir 0
no_sym_pfir 0
msb_pol 0
in_fmt 0
ab_sel 0
input_sel 0
peak_mode 0
peak_threshold 3
peak_sync 5
fine_gain 1070
channel 3
/* copy_channel 0 same as 0 */
/*ch_reset 1*/
phase 0x4000
freq 0x4CCCCCCD
cfir_coef ../Taps/cfir_150.taps
pfir_coef ../Taps/pfir_150.taps
ch_reset 0
use_shift 1
shift 4
freq_sync 7
phase_sync 7
dither_sync 0 /*Original is 4*/
nco_sync 4
zpad_en 0
zpad_sync 4
nzeros 0
flush_sync 4
dec_sync 4
dec 7
gain_sync 7
mix20b 1
big_scale 7
scale 5 /* Changed - ELSEC */
qonly 1
ionly 0
splitiq 1
neg_ctl 0
test 0
coarse 0
idly_cfir 0
qdly_cfir 0
no_sym_cfir 0
peak_select 0
idly_pfir 0
qdly_pfir 0
no_sym_pfir 0
msb_pol 0
in_fmt 0
ab_sel 0
input_sel 0
peak_mode 0
peak_threshold 3
peak_sync 5
fine_gain 1070
/* resampler parameters */
ratio_0 0x04000000
ratio_1 0x04000000
ratio_2 0x04000000
ratio_3 0x04000000
res_coef 0 ../Taps/res_bypass_1024.taps
res_sync 4
nf 0
nc 0
no_sym_res 1
nm 6
filter_sel_3 0
filter_sel_2 0
filter_sel_1 0
filter_sel_0 0
tag_22 0
round 3
final_shift 4
chan_map_d 0
chan_map_c 0
chan_map_b 0
chan_map_a 0
ratio_sync 7
add_c_to_d 0
add_b_to_c 0
add_a_to_b 0
res_clk_div 0
ratio_map 0x00
/* output control */
en_par 1
en_p3 1
en_p2 1
en_p1 1
en_p0 1
en_sfs 1
en_rdy 1
en_sck 1
/* outsync */
out_blk_sync 2
rdy_width 0
tag_en 0
inv_sfs 0
inv_rdy 0
inv_sck 0
/* out format */
reverse_iq 0
output_mode 3
real_only 0
master 1
parallel 1
nibble 0
link 0
/* out frame length */
sfs_mode 2
frame_length 0
/* out word size */
block_size 0
bits_per_word 5
words_per_frame 0
/* out clock */
output_order 0
nserial 0
sck_rate 0
/* serial port selection */
smux_3 3
smux_2 2
smux_1 1
smux_0 0
/* tags */
tag_ai 0
tag_aq 1
tag_bi 2
tag_bq 3
tag_ci 4
tag_cq 5
tag_di 6
tag_dq 7
/* miscellaneous */
en_so 1
en_4_fs 0