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DAC38RF80: about RF sampling transceiver

user5959213
Intellectual 865 points
Part Number: DAC38RF80

hi,all

    I have some questions about DAC's link configuration:

1.This DAC support dual link mode, it means one channel is a link,another channel is another link. Does it need to the LMFS parameter is the same for each link?

2.If i use all the serdes lane,does the lane rate need to be the same of the 8 lane?

3.If I have a requirement that the  two channels have to support different bandwidth,eg.channel 1 is 400M,channel 2 is 500M. Does it support?

Thanks.

  • 0
    TI__Guru 71609 points

    Hi,

    Please find below on answers based on datasheet and register description. The actual usage of the dual link mode under different LMFS setting and SerDes rate will need to be verified based on actual customer demand and system planning.

    1. Not necessarily. The links in dual link mode are technically independent, and can have different LMFS modes

    2. The SerDes rate of all 8 lanes have to be the same due to the programming of the SerDes Configuration 2 register. The single "rate" field applies to all 8 lanes, and all 8 lanes share the same SerDes PLL. Therefore, all 8 lanes have to have the same rate.

    3. Assuming the proper interpolation and JESD modes can applied to the two DUCs available, it is possible for the DAC38RF80 to support different data rate. However, there may limited configuration due to limitation of the same SerDes rate. We may need to recommend set both DUCs to support wide enough bandwidth for both links in this case (i.e. 737.28MSPS to cover both 400MHz and 500MHz BW).

    -Kang

  • 0 in reply to Kang Hsia
    Intellectual 865 points

    Hi Kang,

      Thanks for your prompt reply,I've been obsessed with these concepts lately.

      I have another question,if i use dual DAC,dual link configuration mode,which means 4 lanes per link for a DAC,does this 4 lanes can be divided for a  dual band?

    My usage like this,i have two FPGAs and one DAC38RF80，one FPGA through 4 serdes lanes connects to one DAC for communication and the input data rate is 737.28MSPS, another FPGA through another 4 serdes lanes connects to another DAC for communication and the input data rate is 368.64Msps,which constitutes  dual DAC dual link.In some cases i just need use the first link with another link power down, does this link's 4 lanes can be divided again for a dual band application with each band's input data rate is 368.64MSPS?

      From the  above,you said the two links can have different LMFS parameters,but the serdes rate of each lane of the DACs have to keep the same,so the LMFS have to be the same in practice application?

     Thanks.

  • 0 in reply to user5959213
    TI__Guru 71609 points

    Hello,

    Regarding your question:

    user5959213 said:
    I have another question,if i use dual DAC,dual link configuration mode,which means 4 lanes per link for a DAC,does this 4 lanes can be divided for a  dual band?

    It is possible for dual band configuration per link, as long as the SerDes rate matches between the two links (as mentioned before)

    An example would be the following (in theory pending verification on the silicon)

    all eight lanes will be running at 7372.8Mbps bit rate on the SerDes. On one link with 42111 mode single band, you can configure the DAC core to be 12x interpolation. Another link can be 44210 mode with 24x interpolation, dual band on single DAC. The SerDes rate will remain the same, but the effective LMFS and interpolation will be different between the two link

    We have done so for the AFE76xx device (based on the similar design of the DAC38RF8x device). The DAC38RF8x have similar setup to allow different interpolation setting and internal clock settings (i.e. clk_jesd and clk_jesd_out) for different DAC core. Please take a look at the highlighted LMFS below for an example.