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TRF372017EVM: Carrier leakage optimization

Part Number: TRF372017EVM
Other Parts Discussed in Thread: TRF372017, DAC3283

Hi, I was trying to optimize the carrier leakage on the EVM. The unoptimized leakage level that I measured was -20dBm (see below), which I thought was very high. Here were my test conditions:

> LO freq: 4GHz (internal LO)

> I/Q freq: 400MHz (single tone from sig-gen)

> Vcm: 1.7V (internal, default)

From DS plots, I was expecting this initial unoptimized level to be between -35 and -40dBm. Can you please let me know where you think I might be making a mistake? 

Also, after optimization, I saw only 10dB improvement (see below). Again this seems very little improvement. Can you suggest ways to see more improvement? From another forum post located here, I saw a user get -80dBm at 4.45GHz. How can I get similar performance?

Thanks,

Noman

  • Hi Noman,

    we will go ahead and check here. If you are using the TRF372017 EVM, the default baseband input is AC coupled. Therefore, the DC bias is done through the TRF372017 input bias. Could you please set the baseband inputs to high Z or terminate to double check the LO leakage. If there are differential offsets in the DC, it is possible to impact leakage suppression as well.

    -Kang

  • Hi Kang,

    Ok. I will try your suggestion of terminating the BB inputs tomorrow. I have two additional questions:

    1) If I want to inject external LO from a sig-gen, do I just set the EN_EXTVCO bit high in the GUI or are there other settings also that I need to change?

    2) If I want to inject baseband bias (Vcm) through the sig-gen (i.e. external Vcm), do I just set the PWD_BB_VCM high in the GUI or are there other settings also that I need to change?

    Thank you so much for your help.

    Best regards,

    Noman

  • Hi Kang,

    I was able to get -70 to -80 dBm LO leakage rejection when I injected LO from a sig-gen, i.e. external LO. I was not able to get better than -30dBm when I used internal LO. Is there a leakage path from internal LO to RF_OUT port in the IC that is causing this? If not, then what is the cause of this high level of LO leakage and only a little bit improvement (~10dB) when using the internal DC offset circuits? Has this problem been reported by other customers. Any help in understanding this phenomenon will be greatly appreciated.

    Thanks,

    Noman

  • Hi Norman,

    We have to duplicate this on an EVM to understand the behavior. 4.4GHz performance on this device was not characterized, so we have to do some testing to understand. 

    -Kang

  • Hi Kang,

    Thanks for your support and help in this matter. I measured EVM on TRF372017 evaluation board at 4GHz LO with a 100MHz wide 5GNR DL baseband signal coming from the sig-gen. I injected LO from the same sig-gen at J2 connector (EXT_VCO). I kept the default AC-coupling to the IQ inputs and also used internal Vcm. 

    Firstly I verified my setup by connecting sig-gen straight to VSA. I got the following output spectrum and EVM.

    Next, I connected the TRF272017 evaluation board and got the following spectrum and EVM.

    Couple of things in the last two plots above:

    1) There is a droop from the edges of the signal to the center that is not there when the sig-gen is connected directly to VSA. Do you know why this droop or roll-off is there?

    2) There is noise in the IQ constellation plot that looks unusual to me. Any idea what is causing this noise? I am not using the on-board regulator. So probably its not from there. What other factors that cause it?

    3) Can you share EVM data taken on the evaluation board? Do you think the measured EVM above is higher than what the part is capable of or is it close to what we should expect?

    Thanks,

    Noman

  • Hi, 

    We will need to look into 5G NR data. I am attaching LTE data for the lower LTE bands. I recommend if you can try to duplicate the EVM% on your setup on these RF ranges, then we can establish the baseline for these RF frequencies. We can then move forward to check on the performance of the 4.4GHz LO.

    DAC3283 WCDMA LTE EVM measurement.ppt

  • Hi Kang,

    So I was able to resolve the noisy IQ constellation issue by choosing the option of "Ignore LO Leakage" in the signal analyzer. If you compare the screenshot below with the last screenshot, you can clearly see in the top middle window that the LO leakage has dropped significantly. And with that the noisy IQ constellation issue has also disappeared. Still don't understand the tilt across the channel in the top right window, but will continue to investigate. Any suggestions from your side?

    Also, when do you think you can provide the 5G NR 100MHz DL EVM data on your EVB at 4GHz LO?

    Thanks,

    Noman

  • Hi Noman,

    I will reach out to you separately to understand your application and business case. We currently have limited support on the TRF372017 products at this point.

    I will close out this post and private message you.

    -Kang

  • Sure. I can be reached at noman.paracha@anokiwave.com or 336-554-2649 (cell). Thanks!

  • Hello Noman,

    I have reached out to you offline to discuss the timeline. Please take a look. Thanks.

    -Kang

  • offline discussion on-going.

  • Hi Noman,

    I have tested two types of EVMs: one TRF372017 EVM and one DAC3283 EVM with onboard TRF372017 to interface with the DAC3283. The TRF372017 EVM showed about -30dBm of LO leakage at 4.4GHz, while the DAC3283+TRF372017 EVM showed about -20dBm of LO leakage at 4.4GHz. It is possible this is due to the internal design of the LO and polyphase multiplier network. The behavior on both EVMs are consistent with your observation.

    The Ioffset and Qoffet on both EVMs work as expect to tune out to LO leakage. You will have to find the direction of each offset first, and then gradually dial in each setting to optimize the DC offset correction.

    One suggestion that I have is to use the build-in DC offset correction within the DAC3283 to trim out the DC offset. The DC offset correction on the DAC3283 is finer than the TRF3720 in terms of steps, and may be able to help you suppress/tune out the LO leakage easier. 

    -Kang

  • Hi Kang,

    Thanks for looking into this. Since you have confirmed that the LO leakage is high when using internal synthesizer and that this might be an IC limitation, I want to focus on the 2nd issue now. The 2nd issue is that of high LO leakage with external LO even after the I and Q dc offsets have been optimized through TRF372017 GUI. To me, it seems to be physical LO leakage happening either inside the IC or on PCB. If it’s happening on PCB than I am not concerned. However, if the leakage path is within the IC, then that is definitely a cause for concern. Can you please investigate this issue as well?  The image below elaborates my point.

    Thanks,

    Noman

  • Hi Noman,

    I actually had replied second issue to you via email. 

    The 5G NR specification actually have modulations in the DC to identify different carrier RF range. I believe 1GHz and below has certain BPSK modulation, and 1GHz and above has another BPSK modulation. This is what my R&S support told me. In fact, if your 5G NR waveform going into the modulator has different BPSK identifier for the RF range than the FSW demodulator setting, you will not be able to demodulate properly. This is something you will need to double check with your R&S rep