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AFE8406 ADC Clock input

yuha
Prodigy 70 points
Other Parts Discussed in Thread: CDCM7005

It is planned to form clk by means of clock distribution chips (AD9510 or CDCM7005). How it is better to connect AD9510 and AFE8406?
1. AFE8406 clkp - CMOS CLK
    AFE8406 clkm - ac-coupled with a capacitor
2. AFE8406 clkp - CMOS CLK
    AFE8406 clkm - inverted CMOS CLK
3. LVPECL.

  • 0
    TI__Mastermind 37500 points

    Hello,

    The AFE8406 has an internal dual ADC.  There are upto 2 additional ADCs that can be connected to ports C and D.  The ADC interfacing app notes,

    Normally a differential sine source LvPECL is the lowest noise source.   Please refer to http://focus.ti.com/lit/an/scaa092/scaa092.pdf

     

    Regards,

    Radio Joe

  • 0 in reply to Radio-Joe
    TI__Mastermind 37500 points

    Hello,

    clkpa, clkma, clkpb, clkmb are a differential clock input, transformer coupled from a filtered sine source, or capacitor coupled LvPECL.

    adcclkc, adcclkd are the output data clock from an ADC to the GC5018 / AFE8406.

    Regards,

    Radio Joe

     

  • 0 in reply to Radio-Joe
    Prodigy 70 points

    Hello, Radio-Joe!

    You write:

    - clkpa, clkma, clkpb, clkmb are a differential clock input, transformer coupled from a filtered sine source, or capacitor coupled LvPECL.

    Normally, differential voltage levels for a LVPECL specifications: Vpp = 800 - 1000 mV.

    However, in datasheet AFE8406 p.4  "3.3 RECOMMENDED OPERATING CONDITIONS":

    Analog Chip Differential clock inputs Vpp nom. = 3V.

    How it to understand?

    Whether submission differential LVPECL  is possible or isn't desirable? OR it is better to use single-ended 3.3V CMOS clock?