Other Parts Discussed in Thread: ADC32RF45
Connect the analog board TSW40RF80 to the FPGA board TSW14J57.
The FPGA board has a JESD IP that receives the ADC32RF45 analog board.
It synchronizes only when the config data is downloaded to the FPGA board.
Even if I press the RESET button on the FPGA board and reset the JESD IP, it does not resynchronize.
! The ADC Sync pin setting is the default inversion mode.
After synchronization, use the analog board control software TSW40RF8xEVMGUI.
ADC32RFXX-ADC32RFXX-ADC Configuration tag
ALTEA's Quartus app resynchronizes when Invert SYNC is turned OFF and ON (v).
Monitored with the Signal Tap Logic Analyzer tool.
Even if the SYNC signal of the FPGA board changes from Low (synchronous state) to Hi (asynchronous state), it does not resynchronize.
I monitored the LVDS signal of the SYNC PIN of ADC32RF45 with an oscilloscope and confirmed that it was Hi (asynchronous state) and Low (synchronous state).
It seems that the SYNC pin on the ADC32RF45 is not working.
Is there a condition to put Hi (asynchronous state) of SYNC signal?