Hi,
I have connected the AWR2243boost board via mmwave and FMC adapter boards to an FPGA and would like to configure the board to send the LVDS test pattern at 900Mbps. Up to now I was using the mmWave Studio 3.0.0.14 to do this, but now I want to use the MCU on the FPGA to run the DFP firmware to configure the board to do the same thing.
I have encounted the problem, because I am unable to send the configuration to get the 900Mbps DDR LVDS clock (only 600Mbps).
The following code is from the rl_device.h file from the DFP:
typedef struct rlDevDataPathClkCfg
{
#ifndef MMWL_BIG_ENDIAN
/**
* @brief Clock COnfiguration \n
0 -SDR Clock \n
1 - DDR Clock (Only valid value for CSI2) \n
*/
rlUInt8_t laneClkCfg;
/**
* @brief Data rate selection \n
0001b - 600 Mbps (DDR only) \n
0010b - 450 Mbps (SDR, DDR) \n
0011b - 400 Mbps (DDR only) \n
0100b - 300 Mbps (SDR, DDR) \n
0101b - 225 Mbps (DDR only) \n
0110b - 150 Mbps (DDR only) \n
Others - Reserved \n
*/
rlUInt8_t dataRate;
#else
/**
* @brief Data rate selection \n
0001b - 600 Mbps (DDR only) \n
0010b - 450 Mbps (SDR, DDR) \n
0011b - 400 Mbps (DDR only) \n
0100b - 300 Mbps (SDR, DDR) \n
0101b - 225 Mbps (DDR only) \n
0110b - 150 Mbps (DDR only) \n
Others - Reserved \n
*/
rlUInt8_t dataRate;
/**
* @brief Clock COnfiguration \n
0 -SDR Clock \n
1 - DDR Clock (Only valid value for CSI2) \n
*/
rlUInt8_t laneClkCfg;
#endif
/**
* @brief Reserved for future use
*/
rlUInt16_t reserved;
}rlDevDataPathClkCfg_t;
If I try and enter anything not defined in the above struct I get an "out of the range" error.
Also I have seen in the change log description of the mmWave Radar Interface Control Document (Revision 2.13) that the 900Mbps is removed from the DFP in revision 2.7 (from revision history list):
Removed 900 Mbps (DDR only) data rate in AWR_DEV_RX_
DATA_PATH_CLK_SET_SB API in page 271
What can I do to configure the chip to 900Mbps, the same as I was doing with the mmwave Studio (which uses the same DFP)?
Ivan
