Other Parts Discussed in Thread: TMP116,
Hi all,
for one, i ended up with the same question as in TMP117: Unique ID for NIST traceability - format from the 6 bytes in EEPROM.
Sadly, this was resolved via email, so it would be great to have the response posted here.
The other issue that is bugging me is with EEPROM4:
Even in its revision from April 2021 (SNOSD82C), EEPROM4 is referred to on pages 18 and 30, with page 30 also explicitly mentioning four EEPROM locations.
However, neither the register map nor anything else in the document indicates the address of EEPROM4.
I figured that the TMP116 in fact had 4 EEPROM locations, occupying addresses 0x05 to 0x08.
However, for the TMP117 the register map indicates 0x05, 0x06 and 0x08 for EEPROM1, EEPROM2 and EEPROM3 respectively, while 0x07 is occupied by the Temp_Offset register.
From the addressing scheme, my guess now is that one cell got sacrificed for the Temp_Offset and TMP117 in fact only has three EEPROM cells instead of four with the mentioning of EEPROM4 in the datasheet being a leftover from TMP116. However i can't know for sure and if i am wrong i would like to know the address of EEPROM4.
Can someone please help clarify the issue?
Thanks in advance.
kind regards,