IWR6843: power optimization: can DSS/MSS/BSS subsystems be clock gated/re-clocked

Hello

Have you tried the DSP power gating options.

 Other options you mentioned are not natively supported by device and may cause malfunction.

We would like to understand the scenario better.

Thank you,

Vaibhav

hi,

not tried DSP gating yet. How to do it? Where to find information?

Yes, I understand the latter are nontrivial.

The reasoning is: given the apparent baseline approach is the full power cycling,

for example toggling PMIC enable, which will halt PLL/MSS completely...

maybe there are softer ways to do the same?

The benefit being that Level 3 memories could be carried over to the next measurement cycle?

The scenario/use case is conceptually close to the arrangement descriped in AppNote TIDEP-0091,

except that I am using IWR6843: there is an external microprocessor with  capabilities of data logger, digital and analog control + common constraints of minimal power use..)

which operates the IWR6843 circuit. Thus, the full power cycling could be a principal base line solution.

However there is a challenge of carrying over status and other information (and related overheads in I/O) on the IWR chip

from cycle to another.

Hello

Please look at the TRM for the DSP power domain and the On/Off sequence.

Thank you,

Vaibhav

thank U,

could you decode what the acronym TRM stands for?

.R