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AWR2243: Is there any requirement on the length difference of CSI2 lane trace with 4 AWR2243 chips in cascaded system

Chris Meng
Mastermind 37826 points
Part Number: AWR2243
Other Parts Discussed in Thread: MMWCAS-DSP-EVM

Hi,

We know that the CSI2 lane trace length for one AWR2243 chip should be same. How about the CSI2 lance trace length difference for different chips? What's the max of CSI lane trace length difference with different AWR2243?

Is there any requirement for the FPGA on MMWCAS-DSP-EVM on the length difference with 4 AWR2243 CSI2? My customer is making own 4-chip cascaded RF board and would like to connect to MMWCAS-DSP-EVM. 

  • +1
    TI__Guru 58035 points

    Hello Chris,

    Within the CSI lanes of the device (clk and data), we recommend very good matching (within 25- 50 mils). Between the devices there no strict requirement of length matching as such from 2243 side. It would depend on requirements of the receiver side ( on the processor). If the processor is storing the data from each of the devices totally memory locations then the delay between the devices does not matter. If its storing in the data in an interleaved fashion then you need to make sure the data from all the devices is available within the rate of interleaving.

    Regards,
    Vivek

  • 0 in reply to Vivek Dham
    TI__Mastermind 37826 points

    Vivek,

    The FPGA on MMWAVE-DSP-EVM will convert 4 CSI2 signal to VIP independently, right?

  • +1 in reply to Chris Meng
    TI__Guru 58035 points

    Hello Chris,

    That is correct, on our MMWAVE-DSP-EVM, separate FPGAs and separate VIP ports are used for each device.

    Regards,
    vivek