Hi Experts,
According to an application note "Cascade Coherency and Phase Shifter Calibration" www.ti.com/lit/spracv2, it says below.
Q1). The user how to design the range of temperature for one Bias(such as High Bias)? This there some Important aspects for design the range of temperature to be notice?
Q2). As the note ''allowing a small overlap for transitions'', how long the overlap for transitions is allowed and how to choose the temperatures for the transitions' front and end?
Q3). what's the "transition temperature" means, is it mean the temperature such as 10°C in Low Bias, 0°C and 50°C in Mid Bias, 40°C in High Bias?
Q4). It's maybe the same logic behind the problem as Q2, the application recommended the transitions temperature as close as possible to the factory, how to determining this transitions temperature?
Q5). If the die's temperature from -10°C to 0°C to 10°C to 20°C, when the host transition the Bias, at 0°C (one temperature for Mid Bias) or 10°C (one temperature for Low Bias)? What's more if the temperature from 20°C to 10°C to 0°C to -10°C.
Q6). As the application note use the imbalance Data to be compensated by DSP, which date should be compensated the raw date from ADC or the data after 1dfft or after 2dfft or other?
Q7). Where the residual imbalance mainly come from is it cause by the present temperature different from the factory temperature?
Q8). How can the user obtain this temperature correction LUT, is it obtain from the API after the Phase shift calibration in the RF Init at factory?
Q9). If the user set the Phase Shift: [0, 5, 11, ... , 356] degrees, but the measured [0, 5.623, 11.25, ... , 354.346], how to set the Phase Shift to make the right phase.
