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TMP117: fall time spec of SDA & CLK

Kai Lai
Expert 8856 points
Part Number: TMP117

Hi Team,

My customer is designing TMP117, regarding the SDA fall time spec, it is mentioned that min=20*(V+/5.5), but SCL does not require min in the datasheet.

They are measuring the SDA Fall time and the result is 0.6ns.

1. Can the fall time of SDA be same with SCL without minimum requirements?
    (Customer said someone once said that we can ignore the min requirements of SDA and SCL's rise and fall time. As long as it meets max=300ns)

2. If SDA still has a fall time requirement, the only way is to add capacitance to delay the time ?

Thank you!

Kai

  • 0
    TI__Mastermind 43715 points

    Hi Kai,

    I don't expect this SDA fall time to be an issue. This spec may be referring to the fall time when TMP117 drives the SDA low. There would not be a corresponding fall time spec for SCL, because TMP117 is not capable of driving SCL. The official I2C specification is ambiguous about who is controlling the bus. Some specs don't apply to all devices, but we must write our spec to appear compatible with official spec.

    I would not recommend adding capacitance.

    thanks,

    ren