AWR6843ISK: Power Up Sequence for AWR6843 with LP87524J

Jack

Mastermind 9145 points

Part Number: AWR6843ISK
Other Parts Discussed in Thread: AWR6843, IWR6843ISK

Hi TI

There's a question that Customer wants to clarify.

The following timing diagram is for AWR6843. There's no specific timing values to be followed obviously.

According to EVM schematic, LP87524J PMIC was applied as below.

We want to know the LP87524J comply with AWR6843' wake up sequence below without the customized OTP (or NVM) programming for AWR6843.

Should the OTP with the relevant output timing of each DCDC be used along with customized OTP for AWR6843?

If Not, Did you design only the VIOIN by adding a delay through the Load Switch along with LP87524J's factory default output?

over 4 years ago

0 Jack over 4 years ago

Mastermind 9145 points

Referring

e2e.ti.com/.../2824493

0 Jack over 4 years ago in reply to Jack

Mastermind 9145 points

Ryan Sarver said:

Even the IWR6843ISK doesn't seem to respect this sequence, with VDDIN, VIOIN_18 and VIN_RF all being applied at the same time, and only VIOIN being delayed by the load switch.

Is this correct ? VDDIN, VIO)18 and VIN_RF are supplied at the same time from LP87524J? No need optimized OTP for AWR6843?

Please clarify on this.

Thanks.

Regards,

Jack

0 Ishita Kochar over 4 years ago in reply to Jack

TI__Mastermind 31680 points

Hello Jack,

I believe a similar concern was raised by you last week as well on this : (+) AWR6843ISK: Purpose of Load switch for delaying 3.3V to xWR6843 - Sensors forum - Sensors - TI E2E support forums

I apologize for the delay on this. Our hardware experts our looking into your concern internally. There might be some delay in response due to limited workforce at the moment.

We hope that is okay with you. Thankyou for your patience.

Regards,

Ishita

0 aozer over 4 years ago in reply to Jack

TI__Mastermind 30755 points

Hello Jack,

This is a mistake in the schematic, but it is ok that the 3.3V supply is being delayed after the VDDIN, 1V8, etc. The problem is that NRST is not also being delayed, and is coming up before the 3.3V IO supply, which is violating the timing diagram above.

Please refer to the answer I provided in the thread mentioned by Ishita for a more detailed explanation.

Regards,

Adrian