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AWR6843: Maximum Preload Value of WatchDog

Chen-Chih Liu
Intellectual 340 points
Part Number: AWR6843

Dear experts,

I referred the ticket of https://e2e.ti.com/support/tools/code-composer-studio-group/ccs/f/code-composer-studio-forum/835932/ccs-awr1642boost-awr1642-watchdog-function-to-achieve/3091964#3091964 to implement the Watchdog feature.

The document describes that the range of preload values is between 0 ~ 0xFFF., which means the maximum time expiration is 167.7 ms. 

Q1. May I know the RTICLK1 is 200 MHz (fixed value?)?

Q2. How to implement the Watchdog if cycle time is larger than 167.7 ms?

Sincerely,

Jack

  • 0
    TI__Expert 7510 points

    Jack:

    I am looking into your issue. Give me a couple days to get back to you.

    Best regards,

    Connor Desmond

  • 0
    TI__Expert 7510 points

    Jack:

    Q1. May I know the RTICLK1 is 200 MHz (fixed value?)?

    [CD] >> The clock that drives the DWD peripheral is the RTICLK. This is the clock which feeds the RTI module. As is described in the following thread this clock is a fixed value of 200Mhz, so the maximum cycle time is indeed 167.7ms as you described. I checked at all the registers for this peripheral and there are is no register change that would change the clock.

    Q1. How to implement the Watchdog if cycle time is larger than 167.7 ms?

    [CD] >> As described above the DWD peripheral's clock(RTICLK) is fixed. There are no SW modifications that can happen to change this maximum. The WD threshold's highest value is 0xFFF as described above and the clock can not be changed.

    Best regards,

    Connor Desmond

  • 0 in reply to Connor Desmond
    Intellectual 340 points

    Hi Connor,

    Thanks for your explanation.

    According to your descriptions, the chip has the limitation that we cannot only call the function "Watchdog_clear()" to reset the counter in one cycle if cycle time > 167.7 ms. Will you suggest we can call "Watchdog_clear()" many times during one cycle? Or do you have a better solution for Watchdog implementation?

    Thanks,

    Sincerely,

    Jack

  • 0 in reply to Chen-Chih Liu
    TI__Expert 7510 points

    Jack:

    One thing that you could try to do is set the threshold to a value of your choice e.g. 0xFFF. This will give you a cycle time that is <= to 167.7ms as we have discovered above. Assuming that this cycle time when multiplied by some integer N is equal to the actual cycle time that you are looking for, then you can have a variable that will increment from 0 to N-1 and then once that variable is equal to N you will not call Watchdog_clear(). This is the best solution that I have at this moment.

    Best regards,

    Connor Desmond

  • 0 in reply to Connor Desmond
    Intellectual 340 points

    Dear Connor,

    Sorry that I didn't explain well.

    The definition of one cycle time includes radar sweeping and post-processing. The schematic diagram is shown below.  

    Our application has a longer sweeping time (about 210 ms), which is longer than the maximum WatchDog reset time (167.7 ms).

    In the beginning, my idea is to call the "Watchdog_clear()" at the end of every cycle to clear the WatchDog counter, but the WatchDog reset time is less than our cycle time and this method cannot be used.

    Can we use a "Task" to clear the WatchDog every 50 ms (just an example) to prevent WatchDog reset every time? Is any side effect that we have not considered?

    Thanks,

    Best Regards,

    Jack

  • 0 in reply to Chen-Chih Liu
    TI__Expert 7510 points

    Jack:

    I would definitely try the example you stated above and see if it works! Over all though it is the responsibility of the application to determine when and how to clear the watchdog timer.

    Best regards,

    Connor Desmond