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AWR2243: some questions about the sample rate of AWR2243P

Part Number: AWR2243

Hi all

When i use the chip of AWR2243P, I try to set the adc sample rate to 45Msps. But the firmware is down

And if i decrease the sample rate to 37Msps, it can work normally. So Could you give me some suggestion what's points do i need to check.

My configuration just as below

Thanks

  • Hello User,

    Is your chip AWR2243 or AWR2243P? 

    The max sampling rate in AWR2243P is 45Msps, so technically it should work. In AWR2243, the max rate supported is 37.5Msps. 

    What is the error you're getting if you set it to 45Msps?

    Regards,

    Ishita

  • Hi Ishita

    I see the logo of chip is AWR2243P or XAWR2243P.

    Do i need check any register of the chip ? 

    Thanks

  • This is the value of chip HW version register 

  • if i set to 45Msps, I do not get any error code

    But the LVDS data is all zero .

    Could anyone can help me?

  • Hello Liu, 

    This setting works at our end, so currently I'm not sure of what's happening. Let's try to debug this further. 

    Could you send us your mmwaveconfig.txt file and relevant log info?

    Also, do send a picture of your board as well (want to confirm the presence of AWR2243P chip).

    Regards,

    Ishita

  • Hi Ishita

    Thanks for your reply

    1、The picture of the chip in my board just as below

    2、My config file just as attachment

    mmwaveconfig_OLD.txt
    # DEFAULT ADVANCED CONFIGURATION
    #Power on master config parameters.
    crcType=1
    ackTimeout=1000
    
    #ADC out config parameters. 
    adcBits=2
    adcFormat=2
    
    #DATA format config parameters. 
    adcBitsD=2
    adcFmt=1
    iqSwapSel=0
    chInterleave=0
    
    #Low power config Paramters.
    lpAdcMode=0
    
    #Programmable Filter config parameters. 
    profileIdFilt=0
    coeffStartIdx=0
    progFiltLen=14
    progFiltFreqShift=100
    
    #Data Path config parameters.
    intfSel=1
    transferFmtPkt0=1
    transferFmtPkt1=0
    cqConfig=2
    cq0TransSize=64
    cq1TransSize=64
    cq2TransSize=64
    
    #LVDS clock config parameters.
    laneClk=1
    dataRate=0
    
    #HSI clock parameters.
    hsiClk=13
    
    #LANE config parameters.
    laneEn=15
    
    #LVDS Lane Config parameters.
    laneFmtMap=0
    laneParamCfg=1
    
    #Profile config parameters.
    profileId=0
    startFreqConst=1439117143
    idleTimeConst=6000
    adcStartTimeConst=400
    rampEndTime=1650
    txOutPowerBackoffCode=0
    txPhaseShifter=0
    freqSlopeConst=3107
    txStartTime=0
    numAdcSamples=256
    digOutSampleRate=45000
    hpfCornerFreq1=0
    hpfCornerFreq2=0
    txCalibEnCfg=511
    rxGain=36
    
    #Chirp Configuration parameters.
    chirpStartIdx=0
    chirpEndIdx=0
    profileIdCPCFG=0
    startFreqVar=0
    freqSlopeVar=0
    idleTimeVar=0
    adcStartTimeVar=0
    
    #Frame configuration parameters.
    chirpStartIdxFCF=0
    chirpEndIdxFCF=5
    frameCount=0
    loopCount=128
    periodicity=40000000
    triggerDelay=0
    numAdcSamplesFrame=512
    triggerSelect=1
    
    # CFAR configuration in PL. 
    rangeCfarScaler=2
    dopplerCfarScaler=1
    dopplerCfarEnable=0
    rangePeakEnable=1
    dopplerPeakEnable=0
    
    # Elevation configuration
    useElevation=1
    elevationLimit=30
    
    # Multiple azimuth peaks configuration
    multi_peak_ratio_to_PL=0
    
    # Can Config
    startSendRawDataCan=0
    startSendTrackedDataCan=1
    
    #Monitoring
    monitoringEnable=0
    monitoringReportDelayMs=5000
    
    #Monitoring calibration
    calibMonTimeUnit=100
    
    #Temp Mon configuration parameters.
    TempMonReportMode=2
    TempMonAnaTempThreshMin=-40
    TempMonAnaTempThreshMax=135
    TempMonDigTempThreshMin=-40
    TempMonDigTempThreshMax=135
    TempMonTempDiffThresh=30

  • Hello Liu, 

    Thankyou for the information. 

    Can you let us know the mmWave DFP firmware package you're using here? 

    The latest DFP is 02_02_03_01. I would request you to first use the example as is, and then just modify the 45Msps sampling rate to observe the difference (if any).

    Regards,

    Ishita

  • yes, i have used the 2.2.3.1 MSS version . but if i read the HW version register of the chip, the FW version code also 2.2.1.7. Does TI do not change the version code ?

    1、i think i need change the description of the problem. when i increase the dig output sample rate, i think this problem may something relate to the time or the filter. When the sample rate increase to 35Msps. Although i can get the data from LVDS , but the 1dfft spectrum  is nearly error.

    So could you give me some advise? the two figures just as below is in the same environment.

    fs = 35Msps(error?)

    fs = 30Msps(right)

    Thanks 

  • Hi Ishita

    i think i find the problem. it is something about the programmable filter.

    when i set the filter just as below

    once the sample rate increase to 35Msps, the spectrum will be error

    But when i set the filter as below (i think i bypass the filter)

    Then i can set any sample rate and the spectrum  is right.

    So i see the RAM of filter , i think the coefficient we used is default.

    But i do not understand the filter very clearly so i also do not know why the filter can affect the sample rate?

    Could you give me some suggestion or information?

    Thanks a lot 

  • Please disable the programmable filter if you don't want to use this feature.

    Meanwhile Let me get the reasoning behind this behavior. 

  • OK, Thank a lot,Jitendra

    Look forward to your reply 

  • Hi Jitendra

    Do you have any update?

    Thanks

  • Hi Liu,

    With programmable filter it will bypass some of the ADC sample (frequency band), so when you enable that you see different output compare to when programmable filter is off.

    Please refer ICD to get more detail on programmable filter [Sub block 0x0107 – AWR_PROG_FILT_COEFF_RAM_SET_SB]

    Regards,

    Jitendra