Hi,
I would like to know the max clock for VCLK4 to EPWM. I can't find detail clock source for VCLK4 in TRM. Would you pls kindly help?
Thanks,
Chris
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Hi,
I would like to know the max clock for VCLK4 to EPWM. I can't find detail clock source for VCLK4 in TRM. Would you pls kindly help?
Thanks,
Chris
Hi Chris,
I am checking with our design team for this information. I'll have an answer shortly.
Thank you,
-Randy
Hi Chris,
The ePWM is clocked from the SYSCLK (system clock) which would provide a maximum of 200 MHz for the PWM output frequency. However, the LVCMOS IO used on AM273x have a maximum frequency of 180 MHz, so these will practically limit the frequency.
Thanks,
-Randy