TUSS4440: Increasing the Echo Signal

Hi Carlo,

Thank you for relaying the customer question.

It should be possible to modify some register settings and check to see if the results improve.

 Note, many factors contribute to overall noise, so it can sometimes be difficult to reduce system noise. Generally, the BFP/LPF combined with the proper passive components for CFLT should give a reasonable response. Your waveform SNR looks alright for TOF measurement

To improve the amplitude of the echo return signal, I recommend increasing gain from 15V/V to 20V/V, see Dev_CTRL_2

The settings you are currently using for the threshold are .04(15) +.4 =1V. The threshold for the echo is currently set to 1v, I recommend lowering this to a value that will accurately trigger from the echo signal.

You are correct, the threshold is referenced to ground, so 700mV looks like a reasonable value from the scope shot. Note, it may be necessary to reduce this value a bit to ensure repeatable results.  

This is the AFE for the TUSS44x0 device, Out 3 correspond to a zero crossing comparator with hysteresis.

The purpose of this output is primarily to verify frequency of the signal and offer another direct means for generating an interrupt signal. Most applications do not require the use of OUT3.

Please let me know if you have any questions.

Regards,

Jacob

Lets us say I saw a different frequency ( 50 KHZ) at OUT3 what would be my action? Change frequency of  the driving pulses, adjust the transformer if adjustable, adjust the tuning capacitor?

Hi Fernando,

Thank you for your question,

You can try to change some of the values for the tuning components for the desired frequency output. If you have access to an impedance gain-phase analyzer, you can measure the impedance of the transducer near its operating frequency range to understand the exact frequency to drive at. Additionally, it may be helpful to verify the frequency of the external clock for the transducer.

Please see section 4.4 of slaa732 for a detailed overview of how to optimize the transducer performance.

Please let me know if you have any questions,

Regards,

Jacob

Hello Jacob,

Our customer has follow-up questions. Is 2.60v/v setting 00? Also, the formula is confusing, can you provide an example with the variables filled in?

Also, they have a noise floor of two volts instead of the typical 0.5 volts. Based on their calculations the maximum threshold is 1 or 1.5 volts. 

Please advise, thank you.

Regards,
Carlo

Hi Carlo,

The 2.60 V/V setting correlates with LOGAMP_SLOPE_ADJ setting 0x4

The formula is dependent on the setting for VOUT_SCALE_SELECT, but below represents using 3.0 V/V setting with a gain map of 5V for VOUT_SCALE_SELECT.

Gvout(V/V) = 3.0(5) + 4.56(5) = 37.8V/V

The formula below represents the equation for calculating Vout

The noise floor is a bit high. So long as the return echo is easily distinguishable, there will be no issues. Did the customer already change the LNA gain to be 20V/V?

Thank you,

Jacob

Hello Jacob,

Please see the response of our customer below.

If I use the internal comparator for output via out4 I will have a problem as the voltage level will be higher than the threshold I set in the register. (1.0/1.5) due to the high floor. I would like to know what causes the high noise floor.  It was much lower at one point in time as shown in the previous picture in the original post. I have not changed the hardware.

I thought the gain was the issue so I dropped the gain to the minimum and I still have the same high noise floor. An Alternative would be to use an external comparator but this would be a waste of resources.  On the receive chain I have a 330pf capacitor and 200 ohm resistor however on the data
sheet I am seeing 3.9k resistor in the suggested example. Could this resistor play a part in lowering the floor?

I am operating the device on 5 volts, would operating it on 3.3 volts lower the floor? I am puzzled as to why the floor is so high.
My C filter capacitor is 20nf as I could not find a 15nf.  Then again when I first started, I had a low noise floor but in the process of optimization I now have a ridiculously high noise floor and I am not sure which register caused it. I tried to update all the registers responsible for the output to lower it.
E.g. lowering the gain, lower the slope adj and intercept.  Perhaps I did not pick the lowest slope adj value?

Confirmation of the registers - Write then Read

Appreciate your assistance as I am very close to the end and really need to be able to properly trigger the out4 pin.

Regards,
Carlo

Hi Carlo,

Thank you for relaying the customer message.

Layout can have influence in the noise floor. Did you separate the ground pours for signal ground, and analog ground? Additionally, are these grounds properly connected to one another via a ferrite bead or a single 0-ohm connection? Section 10 of the datasheet covers the grounding technique in more detail.

It is important to use short traces for all connections to the transducer, especially INP and INN.

RINP can be adjusted for EMI rejection. You are welcome to try increasing the resistor.

I do not think changing the supply voltage will change the noise floor. It is important to ensure the supply rail for the device is relatively clean, otherwise, the noise could couple into the receive signal chain. We use a low noise LDO in our EVM design, and we find the low noise performance to be critical to obtain accurate results with the TUSS44x0 devices.

CFLT being 20nF should be alright. Sometimes the value of CFLT may require alteration from the calculated value to optimize performance.

Are you able to revert to a previous documented version of your register settings to verify the higher noise floor was due to register changes? Lowering all registers for the output will likely not make the noise floor lower, in some cases could be making the SNR worse. I recommend using returning to previous register settings if possible.

Regards,

Jacob

Hi Jacob,

Here is the response of our customer.

Jacob Nogaj said:

Layout can have influence in the noise floor. Did you separate the ground pours for signal ground, and analog ground?

Four layer board so digital and analog grounds go straight to the ground plane

Jacob Nogaj said:

Additionally, are these grounds properly connected to one another via a ferrite bead or a single 0-ohm connection? Section 10 of the datasheet covers the grounding technique in more detail.

It is important to use short traces for all connections to the transducer, especially INP and INN.

RINP can be adjusted for EMI rejection. You are welcome to try increasing the resistor.

Used 3k resistor no change.

Jacob Nogaj said:

I do not think changing the supply voltage will change the noise floor. It is important to ensure the supply rail for the device is relatively clean, otherwise, the noise could couple into the receive signal chain. We use a low noise LDO in our EVM design, and we find the low noise performance to be critical to obtain accurate results with the TUSS44x0 devices.

CFLT being 20nF should be alright. Sometimes the value of CFLT may require alteration from the calculated value to optimize performance.

Are you able to revert to a previous documented version of your register settings to verify the higher noise floor was due to register changes? Lowering all registers for the output will likely not make the noise floor lower, in some cases could be making the SNR worse. I recommend using returning to previous register settings if possible.

Not as yet. I am down to a noise floor of 1 volt. The offset is really my issue. Is the 0.4 and 0.6 in the equation the  assumed noise floor/offset?

Your continuous guidance is appreciated.

Regards,
Carlo