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PGA970: S1_CFG register read issue in pga970

Alex Duranti
Prodigy 191 points
Part Number: PGA970

Good morning,

We are experimented PGA970QPHPR writing and reading configuration registers via SPI in Reset mode.

All works fine except S1_CFG readings: when we send the read back command via spi the response includes the value of S1_CFG register not in ADDR position but in ADDr-R+1 position of response message.

Send Command: 0x0044F020

receive  response command: 0x00050102 <- Addr+1 while excpected is Addr

We would like to understand if it is a known behaviour or also for you is an unexpected response.

thank you

  • +1
    TI__Mastermind 31655 points

    Hi Alex,

    Device reads should not straddle a 16 bit address boundary. During a read, the LSB of the address should always be 0 so that the read happens at 16-bit aligned addresses. If you do attempt to read at an address with an LSB of 1, the read may occur as you have seen.

    Please refer to the address row of Table 5 of the datasheet, and the PGA970 Device to SPI Master Response section below it for more information.

    Also note that the read response command should only provide data from address specified in the last read command. In your example the preceding command is a write.

    Regards,

    Scott