Hi supporter:
As the below image shows,we set long idle time for FPGA calculate.We don't know either this long idle time impact the system or not.We know the minimum idle time in document SWRA553A,is there exist maximum idle time?
thanks
thanks~
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Hi supporter:
As the below image shows,we set long idle time for FPGA calculate.We don't know either this long idle time impact the system or not.We know the minimum idle time in document SWRA553A,is there exist maximum idle time?
thanks
thanks~