AWR2944: AWR2944

/**
 *   @file  ADCBuf_HIL.c
 *
 *   @brief
 *      This is the file which demonstrates write and read from ADC Buffer in HIL model  
 *
 *  \par
 *  NOTE:
 *      (C) Copyright 2020 - 2021 Texas Instruments, Inc.
 *
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 *  modification, are permitted provided that the following conditions
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 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
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 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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 */

#include <kernel/dpl/DebugP.h>
#include <kernel/dpl/HwiP.h>
#include <kernel/dpl/ClockP.h>
#include <ti/common/syscommon.h>
#include <drivers/edma.h>
#include <drivers/cbuff.h>
#include "../dssgenerated/ti_board_config.h"
#include "../dssgenerated/ti_board_open_close.h"
#include "../dssgenerated/ti_dpl_config.h"
#include "../dssgenerated/ti_drivers_config.h"
#include "../dssgenerated/ti_drivers_open_close.h"

#include "../../common_includes.h"

#include <string.h>

int32_t dss_ADCBuf_HIL_TC(){
    volatile uint32_t rd_data_HIL[10], addr, count, data_write[10];
    volatile bool flag = true;         

    CSL_rss_ctrlRegs *rssCtrl;
    rssCtrl = (CSL_rss_ctrlRegs *)CSL_RSS_CTRL_U_BASE;

    //Memory intialization of ADCBUF memories 
    CSL_FINS(rssCtrl->RSS_ADCBUF_PING_MEMINIT, RSS_CTRL_RSS_ADCBUF_PING_MEMINIT_RSS_ADCBUF_PING_MEMINIT_START, 0x1);
    while(!(CSL_FEXT(rssCtrl->RSS_ADCBUF_PING_MEMINIT_DONE, RSS_CTRL_RSS_ADCBUF_PING_MEMINIT_DONE_RSS_ADCBUF_PING_MEMINIT_DONE_DONE))==0x1);
    CSL_FINS(rssCtrl->RSS_ADCBUF_PONG_MEMINIT, RSS_CTRL_RSS_ADCBUF_PONG_MEMINIT_RSS_ADCBUF_PONG_MEMINIT_START, 0x1);
    while(!(CSL_FEXT(rssCtrl->RSS_ADCBUF_PONG_MEMINIT_DONE, RSS_CTRL_RSS_ADCBUF_PONG_MEMINIT_DONE_RSS_ADCBUF_PONG_MEMINIT_DONE_DONE))==0x1);

    CSL_FINS(rssCtrl->DMMSWINT1, RSS_CTRL_DMMSWINT1_DMMSWINT1_DMMADCBUFWREN,0x1);

    //Write to the memory location
    for(count = 0; count<10; ++count)
    {
        addr = CSL_RSS_ADCBUF_WRITE_U_BASE+0x4*count;
        WR_MEM_32(addr, 0x12345678+count);
        data_write[count] = 0x12345678+count;
    }

    //Switch write to pong so as to read from ping
    CSL_FINS(rssCtrl->DMMSWINT1, RSS_CTRL_DMMSWINT1_DMMSWINT1_DMMADCBUFPINPONSEL,0x1);

    //Make a read from appropriate RAM location
    for(count = 0; count<10; ++count)
    {
        rd_data_HIL[count] = RD_MEM_32(CSL_RSS_ADCBUF_READ_U_BASE+0x4*count);
    }

    for(count = 0; count<10; ++count)
    {
        if(data_write[count]!=rd_data_HIL[count])
        {
            flag = false;
            break;
        }
    }

    if(flag)
    {
        test_print("ADCBuf HIL mode read and write is correct and successful!!\n");
    }
    else
    {
        test_print("ADCBuf HIL mode read and write is incorrect??\n");
    }

    return 0;

}