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PGA970: Inquiries

Part Number: PGA970

Hi Team,

We have received this inquiries from our customer.

Right now I design an instrument with PGA970 (and other parts so, but I'm okay with them)

I've found it's datasheet, everything is fine. I've also found the evaluation board's document, which was also useful

I'm curious about the pin description of the device. On the IC datasheet the example circuit is different than the one on the EV board. I've found details nowhere.

To mention an exact question how should I determine the values of R and C between the PI and PE pins. On the EV pdf they are simply omitted, although they are referred on the IC datasheet. I've quite the same question for lots of pins.

It's said in the EV pdf, that a serial resistance could be used to form a voltage resistive divider with the input impedance. How big is the input impedance?

What is the output impedance of the LVDT driver? How much load can it handle?

What are the power supply limits; how should I handle the GATE pin of the device?

What is the default configuration of the SPI interface with the factory software?

Can I rely on the factory fw, or I should place SWD to the board and upload a latest version in the manufacturing process?

It would be good to know the input requirements of the amplifiers. In some examples they are DC blocked, in some they does not. I cannot understand which is necessary.

How should the unused analog input handled?

Regards,

Danilo

  • Hello Danilo,

    The RC filter between the PI and PE pins should set a lowpass filter that will not impact the LVDT drive waveform. This will depend on the frequency that their sensor needs to operate.

    I believe the section of the EVM user's guide that mentions a resistor divider is actually referring to the secondary inputs, and not the portion between the PI and PE pins. In this case, the input impedance of the S1 and S2 gain amplifiers is 500kohm.

    I do not have exact specifications for the LVDT gain output, but the absolute max current handling for that pin is 40mA, and the recommend short circuit current is 25mA.

    The power supply limits are described in the specifications with a recommended VDD of 3.5-30V. If the gate pin is not used, connect the GATE pin to ground and disable gate control by setting the GATE_CTRL_SD bit in the ALPWR register to 1. There is more detail in the Gate Drive for N-channel depletion MOSFET section of the datasheet.

    There is no firmware installed on the PGA970 from the TI production facility. That will need to be developed and installed by the user.

    Unused analog inputs like S1x, or S2x should be connected directly to GND.

    Regards,

    Scott

  • Hi Scott,

    Thank you for your response. We have received further inquiries from our customer as follows;

    I know the purpose of the filter. To be able to design it I need the input impedance of the PI pin . (and also the PE-s output, but i suppose it is much lower than the serial I put). Could I suppose that the PI is a high impedance input?

    Thank you for the S1-S2 input impedance.

    Thank you for the output current specification. On which voltage level should it be read?

    Answering 'There is more detail in the Gate Drive for N-channel depletion MOSFET section of the datasheet.'
    I can see this datasheet. www.ti.com/.../pga970.pdf There is no section about this topic. (Nor which power pin could be used until 30 V, nor the impact to logical levels on SPI bus)

    Thank you for the information about the FW.

    Thank you for the information about the unused analog pin.
    I am still uncertain about how should I power the IC (it has several pins). Should they be equal or not, which one determines the logical levels on SPI.

    Regards,

    Danilo

  • Hi Danilo,

    It looks like your customer is not working from the full datasheet for the PGA970. They will need to request access from the PGA970 product page under the heading "More information."

    Regards,

    Scott