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FDC2212-Q1: IO pin status at RESET

Shinji Tsuji
Genius 14099 points
Part Number: FDC2212-Q1

Hi team,

Could you advise the status of the IO port during Rest and after the reset?

SCL/SDA/CLKIN/ADDR/INTB/SD

I would like to know if they are Hi-Z, pull down, pull up. If pull up/down, how much resistance?

regards,

  • 0
    TI__Mastermind 18545 points

    Hello, 

    The SCL and SDA pins will have external pullup resistors on the I2C bus. Unless another device is communicating on the bus, these will be at the pull up voltage.

    If CLKIN is tied to an external oscillator, the status of the pin will be determined by the oscillator. If CLKIN is not used, it should be connected to GND.

    The ADDR pin should either be connected to GND or VDD for the device and will not change. 

    INTB is a push/pull output for the interrupt signal and is de-asserted when the device goes into sleep or shutdown and will not be asserted until and interrupt event happens. This can change depending on how the INTB is configured. For more information on INTB, see section 9.3.4 of the datasheet for status reporting and registers 0x19 (ERROR_CONFIG) and 0x1A (CONFIG) for setting the INTB function. 

    SD is the shutdown input pin and can be connected directly to the MCU. It's state will be determined by the MCU or any external connections (pull up/down or connected to GND for always on). For more information about SD pin, see section 9.4.3 of the datasheet: 

    Best Regards, 

    Justin Beigel

  • 0 in reply to Justin Beigel
    TI__Genius 14099 points

    Hi Justin-san,

    I would like to make sure these pins does or doesn't drive the external circuit during reset and after the reset. 

    SCL/SDA --> High-Z in Reset during reset and after the reset, and no internal pull up/pull-down, correct?  

    CLKIN --> High-Z in Reset during reset and after the reset, and no internal pull-up/down, correct?

    ADDR -->  High-Z in Reset during reset and after the reset, and no internal pull-up/down, correct?

    INTB -->  High-Z in Reset during reset and after the reset, and no internal pull-up/down, correct?

    SD -->  High-Z in Reset during reset and after the reset, and no internal pull-up/down, correct?

    regards,

  • 0 in reply to Shinji Tsuji
    TI__Mastermind 18545 points

    Hello, 

    Shinji Tsuji said:
    SCL/SDA --> High-Z in Reset during reset and after the reset, and no internal pull up/pull-down, correct? 

    Correct. The device does not do anything on these pins until it is communicated to by an MCU. 

    Shinji Tsuji said:
    CLKIN --> High-Z in Reset during reset and after the reset, and no internal pull-up/down, correct?

    Correct. 

    Shinji Tsuji said:
    ADDR -->  High-Z in Reset during reset and after the reset, and no internal pull-up/down, correct?

    Correct. This is just an input and should be tied to VDD or GND externally. 

    Shinji Tsuji said:
    INTB -->  High-Z in Reset during reset and after the reset, and no internal pull-up/down, correct?

    This is an active low output and will be pulled high after reset. If it is disabled, it will remain high. Otherwise, it will operate normally after the device is operating normally. 

    Shinji Tsuji said:
    SD -->  High-Z in Reset during reset and after the reset, and no internal pull-up/down, correct?

    Correct. 

    Best Regards, 
    Justin Beigel