AWR6843: Maximum SPI clock

Kazu

Prodigy 100 points

Part Number: AWR6843

What is the maximum SPI clock when communicating with PC through FTDI?

I read the following test code, but I couldn't understand the maximum SPI clock.

mmwave_sdk_03_05_00_04\packages\ti\drivers\spi\test\common\test_common.c

/* When communicating with PC through FTDI, it is difficult to toggle CS for every two bytes, hence set csHold to 1.

In this mode, the highest working SPI clock is 2MHz */

mmwave_sdk_03_05_00_04\packages\ti\drivers\spi\test\windows\spiTest.cpp

/* Divider low value . 60Mhz/(((high * 256+low)+1)*2)) ,

0xE -> 2MHz SPI clock

0x5 -> 5MHz

0x4 -> 6MHz

0x2 -> 10MHz

0x1 -> 15MHz

0x0 -> 30MHz

txConfBuffer[4] = 0x4;

over 3 years ago

0 Sudharshan KN over 3 years ago

TI__Genius 10550 points

Hi,

The max clock speed supported for SPI on the device is 40MHz (tclk = 25ns). th

Kazu said:
mmwave_sdk_03_05_00_04\packages\ti\drivers\spi\test\common\test_common.c

the above path provides the code for testing the driver. The details of the tests can be found in the test logs located at C:\ti\mmwave_sdk_03_05_00_04\docs\test\IWR68\module_test\xwr68_R4_spi_2020-09-25-08-09-32.log.

The details of the tests are mentioned in mmwave_sdk_03_05_00_04\docs\mmwave_sdk_unit_test_procedure.pdf

Regards,

Sudharshan K N

0 Kazu over 3 years ago in reply to Sudharshan KN

Prodigy 100 points

Hi, Sudharshan,

Thank you for your prompt replay.

I understand that the max clock speed supported for SPI on the device is 40 MHz if the following conditions are met.

If the above conditions are not met, for example, if CS hold is enabled, is the max clock speed still 40 MHz?

I checked the files you told me, but there was no test with CS hold enabled and clock speed set to 40 MHz.

    /* When communicating with PC through FTDI, it is difficult to toggle CS for every two bytes, hence set csHold to 1.
       In this mode, the highest working SPI clock is 2MHz */
    params.csHold = 1;

Best regards,

Kazuya Kimura

0 Sudharshan KN over 3 years ago in reply to Kazu

TI__Genius 10550 points

Hi,

Will check on this and get back to you.

Regards,

Sudharshan K N

0 Sudharshan KN over 3 years ago in reply to Sudharshan KN

TI__Genius 10550 points

Hi,

Since the device uses a Mib-SPI implementation, the toggling of CS is needed after every 16bits.

Regards,

Sudharshan K N

0 Kazu over 3 years ago in reply to Sudharshan KN

Prodigy 100 points

Hi Sudharshan,

Does it mean that the max clock speed is not 40 MHz when CS hold is enabled?

Best regards,

Kazuya Kimura

+1 Sudharshan KN over 3 years ago in reply to Kazu

TI__Genius 10550 points

Hi,

The clock speed can be 40MHz. The only limitation seems to be with the CS toggle.

Regards,

Sudharshan K N

0 Kazu over 3 years ago in reply to Sudharshan KN

Prodigy 100 points

Hi Sudharshan,

Thank you for your reply.

I understand the limitation.

Best regards,

Kazuya Kimura

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AWR6843: Maximum SPI clock