AWR2243: Why to use the 40MHz clock buffer in AWR2243 4 chip cascade design

Hi Cesar:

Thanks for your reply.

For the 77GHz/20GHz LO signal they are all from the master 2243, so it's not relevant to what 40MHz we feed to slave 2243s

For ADC start time, they are triggered by Digital Sync (dedicate Sync_in Sync_out pins and buffer), so they don't count on "same 40MHz as well".

"SWRA574B" says "(for this 40MHz clock) There is no phase/delay matching requirements on this clock." 

I wonder what exactly type of synchronization is relying on the fact that all 40MHz's for 2243s are from the same source?

Reason I'm digging on this question is that the pin CLKP seems not to be designed for connecting to a high speed transmission line, it has high impedance input, and we observed noticeable waveform distortion on this 40MHz square wave between the clock buffer and the 2243 (even on TI reference design). And have 3 additional crystals near each 2243 not only simplify the routing, it's cheaper too... 

Hi,

I will ask the HW team to review this question

thank you

Cesar

Hi,

       The 40MHz topology in the EVM is to indicate that you can have a single clock source to feed all the devices. The capapbility of OSC_CLK_OUT form Primary device facilitates user to reuse single XTAL for cascaded devices. If you wish to use the separate XTAL's for all devices its your choice. However, keeping single clock source has more control.

Regards

Hi Abhed,

could you please elaborate on "keeping single clock source has more control"?

Am I right above that neither the sync of the 20GHz LO nor ADC start time is relying on "single clock"? What exactly is the benefit of having the same clock source? 

Thanks,

Li

Hi Li,

         With 40MHz clock coming from primary, the probability of localized slave level XTAL failure is eliminated. Secondly, clock from primary will be much more cleaner. 

Regards

Abhed: 

Sorry but I cannot make sense of what you said:

1. Is XTAL failure something happens often? If that's the case, the master will have this issue as well? Plus,  I cannot see why it's more reliable using single XTAL source for all 2243 plus the circuitry of LMK00804 and all the traces...

2. Have you ever measure the 40MHz clocks on TI dev board? for some reason I cannot attach the OSC screen shot now, but the waveform from the 43Ohm series matched resistor to the slave AWR2243s are heavily distorted (discontinuity on the rising and falling edges), and the reason (I've mentioned above) is the XTAL high input impedance. The output from master 2243 maybe "cleaner", but due to mismatched impedance, the slave 2243's XTAL is not designed for being driven with long traces.

Hi,

1. I used the term localized secondary device XTAL failure, indicating that in that case the Primary device will have to identify/detect and anyways would categorize to gross failure of system. With single XTAL sourcing topology also in case of XTAL failure it will be gross, but would be easily detectable by HOST.

However, you can use individual XTAL's if you board design permits.

2. We have done measurements for the RF performance of the device on EVM. The results are included int eh design guide. 

The external clock specs are listed in datasheet, which needs to be followed for desired performance from the device.

Regards