PGA970: Low amplitude on waveformgeneration

Hi Paul,

The internal Primary supply gain stage can be adjusted, but the gain only goes up to 1.67V/V, which would not account for the difference between 40mV and 700mV. Are you certain that all of the waveform DAC output stage settings are the same between your EVM setup and the custom board setup? The main place to look would be in the LVDT_OP_CTRL register.

Regards,

Scott

Hi Scott,
The odd thing is, im measuring the Waveformsignal on my testboard after the amplifier. This results in the same signal the EVM gives directly at P1 and P2.
LVDT_OP_CTRL is set at 0x80 on both boards.
I provided the list with registers and their values of my testboard. The ones that are marked yellow are differnt to those on the EVM. I listed the corresponding values of the EVM below.


Testboard:

PGA970 CSR    PGA970 Control and Status Registers    
    [0 ... 99]    
        RAMBIST_CONTROL                   0x0C     RAM Memory Built-In Self-Test Control Register [Memory Mapped]    
        RAMBIST_STATUS                        0x08    RAM Memory Built-In Self-Test Status Register [Memory Mapped]    
        CLK_CTRL_STATUS                     0x33    M0 Frequency Control Register [Memory Mapped]    
        FRAM_STATUS                              0x00    FRAM Parity check status Register [Memory Mapped]    
        DIG_IF_CTRL                                 0x05    Digital Interface Control Register [Memory Mapped]    
        OWI_ERROR_STATUS_LO           0x00    OWI Error Status Low Register [Memory Mapped]    
        OWI_ERROR_STATUS_HI            0x00    OWI Error Status High Register [Memory Mapped]    
        OWI_INTERRUPT                          0x00    OWI Interrupt Status Register [Memory Mapped]    
        OWI_INTERRUPT_ENABLE        0x00    OWI Interrupt Control Register [Memory Mapped]    
        FRAM_PAGE_ADDR                     0x00    FRAM Page Address Register [Memory Mapped]    
        DATA_WAVE_PAGE_ADDR         0x00    Data Waveform Page Address Register [Memory Mapped]    
        DEVRAM_PAGE_ADDR               0x00    Development RAM Page Address Register [Memory Mapped]    
        WDOG_CTRL_STAT                      0x00    Watchdog Control and Status Register [Memory Mapped]    
        WDOG_TRIG_HIGH                      0xFF    Watchdog High Trigger Register [Memory Mapped]    
        WDOG_TRIG_LOW                       0x80    Watchdog Low Trigger Register [Memory Mapped]    
        DEMOD1_CONFIG                        0x07    DEMOD1 Configuration Register [Memory Mapped]    
        DEMOD2_CONFIG                        0x07    DEMOD2 Configuration Register [Memory Mapped]    
        ADC3_CONFIG                               0x03    ADC3 Configuration Register [Memory Mapped]    
        S1_S2_DEMOD_CFG_1                 0x08    S1 S2 DEMOD Configuration Register [Memory Mapped]    
        S3_ADC_CFG_1                              0x08    S3 ADC Configuration Register [Memory Mapped]    
        S1_CFG                                            0x00    S1 Configuration Register [Memory Mapped]    
        S2_CFG                                            0x00    S2 Configuration Register [Memory Mapped]    
        S1_S2_CFG                                      0x04    S1 S2 Configuration Register [Memory Mapped]    
        S3_CFG                                            0x00    S3 Configuration Register [Memory Mapped]    
        S3_CFG_1                                        0x00    S3 Configuration Register_1 [Memory Mapped]    
        DAC_REG0_1                                  0x00    DAC Register0_1 [Memory Mapped]    
        DAC_REG0_2                                  0x00    DAC Register0_2 [Memory Mapped]    
        DAC_CTRL_STATUS                      0x31    DAC Control and Status Register [Memory Mapped]    
        DAC_CONFIG                                 0x00    DAC Configuration Register [Memory Mapped]    
        DAC_LPBK_CTRL                          0x00    DAC Loopback Control Register [Memory Mapped]    
        OP_STAGE_CTRL                           0x11    DAC Output Stage Control Register [Memory Mapped]    
        LVDT_OP_CTRL                             0x80    LVDT Configuration Register [Memory Mapped]    
        LVDT_LPBK_CTRL                        0x00    LVDT Loopback Configuration Register [Memory Mapped]    
        CCS_CTRL                                       0x00    Constant Current Source Configuration Register [Memory Mapped]    
        AFEDIAG_CFG                                0x00    AFEDIAG Configuration Register [Memory Mapped]    
        ALPWR                                             0x04    ALPWR Register [Memory Mapped]    
        DLPWR                                             0x00    DLPWR Register [Memory Mapped]    
        PSMON1                                           0x08    PSMON1 Fault Detect Register [Memory Mapped]    
        PSMON2                                           0x10    PSMON2 Fault Detect Register [Memory Mapped]    
        AFEDIAG                                          0x02    AFEDIAG Register [Memory Mapped]    
        AFEDIAG1                                        0x00    AFEDIAG1 Register [Memory Mapped]    
        AFEDIAG3                                        0x33    AFEDIAG3 Register [Memory Mapped]    
        AFEDIAG4                                        0x30    AFEDIAG4 Register [Memory Mapped]    
        TOPDIG_MUX_SEL                        0x00    TOPDIG Multiplexer Register [Memory Mapped]    
        AMUX_ACT                                     0x00    Analog Multiplexer Activate Register [Memory Mapped]    
        AMUX_TIN_MUX_CTRL               0x00    TIN Analog Multiplexer Register [Memory Mapped]    
        AMUX_TOUT_MUX_CTRL           0x00    TOUT Analog Multiplexer Register [Memory Mapped]    
        AMUX_CTRL                                   0xFF    Analog Multiplexer Register [Memory Mapped]    
        WAVEFORM_GEN_CTRL              0x03    Waveform Generation Control and Status Register [Memory Mapped]    
        WAVEFORM_TABLE_LEN             0x18    Waveform Table Length Register [Memory Mapped]    
        WAVEFORM_DAC_OFFSET_0      0x08    Waveform DAC Offset Register_0 [Memory Mapped]    
        WAVEFORM_DAC_OFFSET_1      0x2C    Waveform DAC Offset Register_1 [Memory Mapped]    
        FAST_DIV_NUMERATOR_1          0xF7    FAST_DIV_NUMERATOR_1 Register [Memory Mapped]    
        FAST_DIV_NUMERATOR_2          0xFF    FAST_DIV_NUMERATOR_2 Register [Memory Mapped]    
        FAST_DIV_NUMERATOR_3          0xFF    FAST_DIV_NUMERATOR_3 Register [Memory Mapped]    
        FAST_DIV_NUMERATOR_4          0xFF    FAST_DIV_NUMERATOR_4 Register [Memory Mapped]    
        FAST_DIV_DENOMINATOR_1     0x00    FAST_DIV_DENOMINATOR_1 Register [Memory Mapped]    
        FAST_DIV_DENOMINATOR_2     0x00    FAST_DIV_DENOMINATOR_2 Register [Memory Mapped]    
        FAST_DIV_DENOMINATOR_3     0x00    FAST_DIV_DENOMINATOR_3 Register [Memory Mapped]    
        FAST_DIV_DENOMINATOR_4     0x00    FAST_DIV_DENOMINATOR_4 Register [Memory Mapped]    
        FAST_DIV_CTRL                            0x00    FAST_DIV Control Register [Memory Mapped]    
        FAST_DIV_STAT                             0x03    FAST_DIV Status Register [Memory Mapped]    
        FAST_DIV_QUOTIENT_1              0x01    FAST_DIV_QUOTIENT_1 Register [Memory Mapped]    
        FAST_DIV_QUOTIENT_2              0x00    FAST_DIV_QUOTIENT_2 Register [Memory Mapped]    
        FAST_DIV_QUOTIENT_3              0x00    FAST_DIV_QUOTIENT_3 Register [Memory Mapped]    
        FAST_DIV_QUOTIENT_4              0x00    FAST_DIV_QUOTIENT_4 Register [Memory Mapped]    
        FAST_DIV_REMAINDER_1          0xF7    FAST_DIV_REMAINDER_1 Register [Memory Mapped]    
        FAST_DIV_REMAINDER_2          0xFF    FAST_DIV_REMAINDER_2 Register [Memory Mapped]    
        FAST_DIV_REMAINDER_3          0xFF    FAST_DIV_REMAINDER_3 Register [Memory Mapped]    
        FAST_DIV_REMAINDER_4          0xFF    FAST_DIV_REMAINDER_4 Register [Memory Mapped]    
        DEMOD1_BPF_B1_1                      0x95    DEMOD1_BPF_B1_1 Register [Memory Mapped]    
        DEMOD1_BPF_B1_2                      0x14    DEMOD1_BPF_B1_2 Register [Memory Mapped]    
        DEMOD1_BPF_B1_3                      0x00    DEMOD1_BPF_B1_3 Register [Memory Mapped]    
        DEMOD1_BPF_A2_1                      0x18    DEMOD1_BPF_A2_1 Register [Memory Mapped]    
        DEMOD1_BPF_A2_2                      0xCB    DEMOD1_BPF_A2_2 Register [Memory Mapped]    
        DEMOD1_BPF_A2_3                      0xFF    DEMOD1_BPF_A2_3 Register [Memory Mapped]    
        DEMOD1_BPF_A3_1                      0xD6    DEMOD1_BPF_A3_1 Register [Memory Mapped]    
        DEMOD1_BPF_A3_2                      0xD6    DEMOD1_BPF_A3_2 Register [Memory Mapped]    
        DEMOD1_BPF_A3_3                      0xFF    DEMOD1_BPF_A3_3 Register [Memory Mapped]    
        DEMOD1_LPF_B1_1                      0xF3    DEMOD1_LPF_B1_1 Register [Memory Mapped]    
        DEMOD1_LPF_B1_2                      0x04    DEMOD1_LPF_B1_2 Register [Memory Mapped]    
        DEMOD1_LPF_A2_1                      0x19    DEMOD1_LPF_A2_1 Register [Memory Mapped]    
        DEMOD1_LPF_A2_2                      0x76    DEMOD1_LPF_A2_2 Register [Memory Mapped]    
        DEMOD2_BPF_B1_1                      0x6E    DEMOD2_BPF_B1_1 Register [Memory Mapped]    
        DEMOD2_BPF_B1_2                      0x33    DEMOD2_BPF_B1_2 Register [Memory Mapped]    
        DEMOD2_BPF_B1_3                      0x00    DEMOD2_BPF_B1_3 Register [Memory Mapped]    
        DEMOD2_BPF_A2_1                      0x47    DEMOD2_BPF_A2_1 Register [Memory Mapped]    
        DEMOD2_BPF_A2_2                      0xAC    DEMOD2_BPF_A2_2 Register [Memory Mapped]    
        DEMOD2_BPF_A2_3                      0xFF    DEMOD2_BPF_A2_3 Register [Memory Mapped]    
        DEMOD2_BPF_A3_1                      0x23    DEMOD2_BPF_A3_1 Register [Memory Mapped]    
        DEMOD2_BPF_A3_2                      0x99    DEMOD2_BPF_A3_2 Register [Memory Mapped]    
        DEMOD2_BPF_A3_3                      0xFF    DEMOD2_BPF_A3_3 Register [Memory Mapped]    
        DEMOD2_LPF_B1_1                      0x05    DEMOD2_LPF_B1_1 Register [Memory Mapped]    
        DEMOD2_LPF_B1_2                      0x01    DEMOD2_LPF_B1_2 Register [Memory Mapped]    
        DEMOD2_LPF_A2_1                      0xF5    DEMOD2_LPF_A2_1 Register [Memory Mapped]    
        DEMOD2_LPF_A2_2                      0x7D    DEMOD2_LPF_A2_2 Register [Memory Mapped]    
        ADC3_VI_LPF_B1_1                      0x4A    ADC3_VI_LPF_B1_1 Register [Memory Mapped]    
        ADC3_VI_LPF_B1_2                      0x07    ADC3_VI_LPF_B1_2 Register [Memory Mapped]    
        ADC3_VI_LPF_A2_1                      0x6C    ADC3_VI_LPF_A2_1 Register [Memory Mapped]    
        ADC3_VI_LPF_A2_2                      0x71    ADC3_VI_LPF_A2_2 Register [Memory Mapped] 

Registers read on the evaluationboard are following below ( only including the yellow marked registers above)    

PGA970EVM:

RAMBIST_CONTROL                           0x00    RAM Memory Built-In Self-Test Control Register [Memory Mapped]    
RAMBIST_STATUS                               0x00    RAM Memory Built-In Self-Test Status Register [Memory Mapped]    
FRAM_STATUS                                      0x02    FRAM Parity check status Register [Memory Mapped]    
PSMON1                                                  0xA8    PSMON1 Fault Detect Register [Memory Mapped]    
AFEDIAG                                                0x12    AFEDIAG Register [Memory Mapped]    
FAST_DIV_NUMERATOR_1                0xFF    FAST_DIV_NUMERATOR_1 Register [Memory Mapped]    
FAST_DIV_DENOMINATOR_1           0xFF    FAST_DIV_DENOMINATOR_1 Register [Memory Mapped]    
FAST_DIV_DENOMINATOR_2           0xFF    FAST_DIV_DENOMINATOR_2 Register [Memory Mapped]    
FAST_DIV_DENOMINATOR_3           0xFF    FAST_DIV_DENOMINATOR_3 Register [Memory Mapped]    
FAST_DIV_DENOMINATOR_4           0xFF    FAST_DIV_DENOMINATOR_4 Register [Memory Mapped]    
FAST_DIV_STAT                                   0x01    FAST_DIV Status Register [Memory Mapped]    
FAST_DIV_REMAINDER_1                0x00    FAST_DIV_REMAINDER_1 Register [Memory Mapped]    
FAST_DIV_REMAINDER_2                0x00    FAST_DIV_REMAINDER_2 Register [Memory Mapped]    
FAST_DIV_REMAINDER_3                0x00    FAST_DIV_REMAINDER_3 Register [Memory Mapped]    
FAST_DIV_REMAINDER_4                0x00    FAST_DIV_REMAINDER_4 Register [Memory Mapped]    

Regards,
Paul
 

Hi Scott,
did you find something that might cause this problem?

Regards,
Paul

Hi Paul,

It looks like you have an AVDD overvoltage fault detected by the part (PSMON1 register). What voltage do you read on AVDD?

Regards,

Scott

Hi Scott,
My AVDD voltage is 3,3V on the testboard i made myself. However the PSMON1 0xA8 is written onto the PGA970EVM it indeed has too low AVDD voltage with exactly 3V. I didn't do a great job Highlighting that the bottom like 15 registers belong to the evaluationboard. I fixed that in my previous post.

So the correctly working evaluationboard has more faults deteced than my not as intended working testboard.
I reset the PSMON1 register on my own testboard to see if the value 0x08 returns which states REV_UV but it didn't. So is my non fault detecting board the problem why my amplitude of my wavesignal is too low?! That doesn't sound right.


Also I realised that the Amplitude is roughly 16 times smaller compared to what im measuring on the Evaluationboard but this already occurs before the wavesignal even reaches the amplifier. This leads to the rather weird situation of my amplified waveform on the testboard beeing roughly the same as the waveform measured on the evaluationboard at the Pins P1 and P2.

Regards,
Paul

Hi Paul,

The AVDD is internally generated, and should be 3V. Sometimes the power supply faults can appear initially at powerup, and just need to be cleared. I just wanted to check with you that the part was powered correctly, and the simplest way is to check that the outputs of the internal regulators are correct.

Do you have a full schematic that you can share? Feel free to message me if you don't want it posted publicly. You mention that AVDD is at 3.3V, which is pretty high. The threshold for the AVDD_OV is actually set at 3.3V. As I mentioned, the AVDD is internally generated, and should be very close to 3V normally, so something else may be going on here.

As a side note, I will be out of the office from the 25th to July 4th, so I will be able to respond again when I am back in the office on July 5th.

Regards,

Scott

Hi Scott,
I sent you the file via direct message.
Regards,
Paul

Hi, Scott did you recive my message?
Did you have a look at it already?
Regards,
Paul

Hi Paul,

I did get your message. I'm taking a look and I will get back to you soon.

Regards,

Scott