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AWR2243: The output data about AWR2243-LVDS-HSI-test-mode is abnormal

liao junsen
Prodigy 10 points
Part Number: AWR2243

LVDS interface can be tested by using TESTPATTERN function. It is found that two of the four LVDS data channels of AWR2243 have abnormal data phenomenon .

I set four channels in the code, and all IQ outputs fixed data 5A5A(for binary is 0101 1010 0101 1010), but the actual output data in channel 1 and channel 2 will show two fixed error values after being analyzed by FPGA, one is 2D2D(for binary is 0010 1101 0010 1101) and the other is B4B4(for binary is 1011 0100 1011 0100) . The data in channel 3 and channel 4 are normal.  The actual output data of LVDS channel 1 and channel 2 were captured by oscilloscope, and it was found that the data was indeed abnormal, and the outlier value was the same as that parsed by FPGA. May I ask what causes this phenomenon? Is it related to the PCB layout wiring of LVDS? 

  • 0
    TI__Guru 58035 points

    Hello,

    Can you share the exact configuration used to configure the test pattern? Also can you share the oscilloscope plot snapshots?

    Regards,
    Vivek

  • 0 in reply to Vivek Dham
    Prodigy 10 points

    parameter confige as follows：

    #ifdef HSI_TEST_ENABLE

    int MMWL_HSItestCfg(unsigned int deviceMap)

    {
    int32_t retVal = 0;
    rltestPattern_t hsitestdata;
    hsitestdata.testPatGenCtrl = 1;

    hsitestdata.testPatGenTime = 100;
    hsitestdata.testPatrnPktSize = 64;
    hsitestdata.numTestPtrnPkts = 0;
    hsitestdata.testPatRx0Icfg = 0x00005a5a;
    hsitestdata.testPatRx0Qcfg = 0x00005a5a;
    hsitestdata.testPatRx1Icfg = 0x00005a5a;
    hsitestdata.testPatRx1Qcfg = 0x00005a5a;
    hsitestdata.testPatRx2Icfg = 0x00005a5a;
    hsitestdata.testPatRx2Qcfg = 0x00005a5a;
    hsitestdata.testPatRx3Icfg = 0x00005a5a;
    hsitestdata.testPatRx3Qcfg = 0x00005a5a;
    retVal = rlDeviceSetTestPatternConfig(deviceMap, &hsitestdata);
    return retVal;

    }

    The configuration sequence as follows：


    retVal = MMWL_dataPathConfig(deviceMap);
    if (retVal != RL_RET_CODE_OK)
    {

    #ifdef UART_DEBUG_INFO
    UART_WriteStr(UART0,"MMWL_dataPathConfig fail!!!\n\r");
    #endif

    return -1;
    }
    #ifdef UART_DEBUG_INFO

    UART_WriteStr(UART0,"MMWL_dataPathConfig success!!!\n\r");
    #endif

    #ifdef HSI_TEST_ENABLE
    retVal = MMWL_HSItestCfg(deviceMap);

    if (retVal != RL_RET_CODE_OK)
    {
    #ifdef UART_DEBUG_INFO

    UART_WriteStr(UART0,"MMWL_HSItestCfg fail!!!\n\r");
    #endif
    return -1;

    #ifdef UART_DEBUG_INFO
    UART_WriteStr(UART0,"MMWL_HSItestCfg success!!!\n\r");
    #endif

    #endif

    retVal = MMWL_hsiClockConfig(deviceMap);
    if (retVal != RL_RET_CODE_OK)
    {

    #ifdef UART_DEBUG_INFO
    UART_WriteStr(UART0,"MMWL_hsiClockConfig fail!!!\n\r");
    #endif

    return -1;
    }
    #ifdef UART_DEBUG_INFO

    UART_WriteStr(UART0,"MMWL_hsiClockConfig success!!!\n\r");
    #endif

    #ifdef UART_DEBUG_INFO
    UART_WriteStr(UART0,"MMWL_hsiLaneConfig fail!!!\n\r");

    #endif
    return -1;
    }
    #ifdef UART_DEBUG_INFO

    UART_WriteStr(UART0,"MMWL_hsiLaneConfig success!!!\n\r");
    #endif

  • 0 in reply to Vivek Dham
    Prodigy 10 points

    The oscilloscope test waveforms (FR and channel 1 data) are shown below

  • 0 in reply to liao junsen
    TI__Genius 9330 points

    Hi，

    Suggest u move the retVal = MMWL_HSItestCfg(deviceMap); after all LVDS cfg include data path, clock and lane cfg, ensure the LVDS is configured well before test pattern cfg, similar with the test source cfg in the cascade example, then try again. thanks.

    Andy

  • 0 in reply to Andy Yin
    Prodigy 10 points

    hello，andy

                    move the retVal = MMWL_HSItestCfg(deviceMap);after all LVDS cfg include data path, clock and lane cfg, Start the configuration of MMWL_HSItestCfg,I get the same result , the data of chanel 1 and chanel is unusual.

  • 0 in reply to liao junsen
    TI__Guru 58035 points

    Hello ,

    I assume the waveform captures channel 1 P and M lines. How does this waveform compare to a good channel where you are getting the right data ? Do you see a skew/delay between the channel data ?

    regards,

    vivek 

  • 0 in reply to Vivek Dham
    Prodigy 10 points

    The correct channel data was determined, but no oscilloscope was used to capture the corresponding waveform

  • 0 in reply to liao junsen
    TI__Guru 58035 points

    Hello Liao,

    I recommend to probe the LVDS channels on the scope to see if the data on the LVDS lines show the bit shift you are seeing in the captured data. I suspect the issue is on the capture system. 

    Regards,
    vivek 

  • 0 in reply to Vivek Dham
    TI__Genius 9330 points

    Vivek,

    The issue is solved, problem is at their FPGA software, thanks for your support.

    Andy

  • 0 in reply to Vivek Dham
    Prodigy 10 points

    hello Vivek,

    The issue is solved,  thanks for your support