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AWR2944 Exception table linking

Mahmoud Russelan
Prodigy 40 points
Other Parts Discussed in Thread: AWR2944

Hello team,

We have a question regarding the linking of the Exception Table for R5F core within AWR2944. Is there any limitation to link the Exception table to a specific Address ?

More specifically , Can we map the exception table not in Address 0x0 and not in TCMA_ROM_CR5A ? , or we have to have the Exception table mapped to Address 0x0 within TCMA_ROM_CR5A?

Best Regards,

Russel

  • 0
    TI__Guru 70060 points

    Hi Russel,

    On 0th address, mostly you keep interrupt vector tables (IVT) and from there you can navigate your individual exception.

    RTOS takes care of exception handling, are you not using OS with your application??

    Regards,

    Jitendra

  • 0 in reply to Jitendra Gupta
    Prodigy 40 points

    Hello ,

    Thanks for your feedback , thanks for the correction, yes we are asking about the (IVT), is it "mostly" or "must" as our observation whenever an exception happen it jumps to the IVT in address 0x0.

    In our situation, we have three different software with different exception handlers memory space,but we want to have the every software to have its own ExcVec in its own memory address.

    Is that feasible ?

    Best Regards,

    Russel

  • 0 in reply to Mahmoud Russelan
    TI__Mastermind 36515 points

    Hi Russel,
    So if you want to run multiple applications, the SBL needs to take care of mapping the 0th address IVT to the application Vector Table.
    It is not possible to assign the IVT table to another location, so its not possible for every software to have its own ExcVec.
    This mapping needs to be done whenever the bootloader loads a different application

    Regards,
    Saswat