AWR2944: Warm reset is reinitializing the MSS_L2 and DSS_L3 RAM

Mahmoud Russelan

Part Number: AWR2944

Hello Team,

We are using the MCU_PerformReset() and we are configuring the reset mode to "MCU_PERFORM_RESET_MODE_WARM" we are expecting as per the datasheet that our RAM values will not by initilaized (reset to zero) .

But we are noticing is that after the MCU_PerformReset() and before jumping to the SBL the RAM is cleared. could you please confirm that if this is the expected behavior or not ?

In our scenario we need to reset from the application and trigger the SBL again to load the Application without touching the RAM variables.

we have checked the following issue :

AWR2944: AWR2944 software reset - Sensors forum - Sensors - TI E2E support forums

and it is mentioned there that we can invoke the function:

SOC_rcmR5TriggerReset() , when we trigger this function we notice that the Software is being reset to the entry point with no changes in the RAM variables but the SBL was not triggered .

Could you please advice how can we Trigger the SBL again (the same behavior from the MCU_PerformReset() but keep the value of the RAM)?

Best Regards,

Russel

over 3 years ago

0 Stefan_Haas over 3 years ago

TI__Mastermind 25252 points

Hello Russel,

For SOC_rcmR5TriggerReset():

I believe Mounir mentioned on Friday that during the SBL execution some parts are overwritten, thus after a first time SBL execution the initialization is not identical to the initialization fresh out of a first time boot ROM execution.

Can you additionally provide the code reference on how you try to set the entry point? Also in the complete program flow up to SOC_rcmR5TriggerReset().

Ajay,

Just to clarify: the customer would like to execute SBL a second time, with slightly different configuration but keeping the SBL in RAM w/o a reload from flash. So the question is:

- how to best achieve that w/o POR so the RAM content is not reset?

- if above idea comes closest... what needs to be reinitialized so the SBL has an identical HW/SoC initialization like fresh out or POR and boot ROM execution?

Thanks, Stefan

0 Mahmoud Russelan over 3 years ago in reply to Stefan_Haas

Prodigy 40 points

Hello Stefan Haas,

We succeeded today temporally to perform the reset by copying the content of the vector table of the SBL to address 0x0 and then perform SOC_rcmR5TriggerReset();

but is there another way to achieve this behavior , as we just copied the content of the TCMA from the SBL and then copied it while the application is running and afterwards performed the SOC_rcmR5TriggerReset().

Another point is that as this is an Autosar project we need to use the MCU_PerformReset() , for the long run , how is that feasible ?

Best Regards,

Russel

0 Ajay Narayan over 3 years ago in reply to Mahmoud Russelan

TI__Mastermind 22605 points

Hi,

If the aim is to re-run the SBL with a different config and you want some RAM memory which will not be erased/reinitialized on warm reset, then that can be done using the retention RAM.

MSS_RETRAM, start: 0xC5010000, size 2KB

But you need to initialize the RET RAM every time after POR and it will retain contents over warm reset and no need to re-initialize it during warm reset.

Code example to to initialize ret ram:

volatile uint32_t *MSS_CTRL_MSS_RETRAM_MEM_INIT =(uint32_t*)0x0212004C;
volatile uint32_t *MSS_CTRL_MSS_RETRAM_MEM_INIT_DONE = (uint32_t*)0x02120050;

*MSS_CTRL_MSS_RETRAM_MEM_INIT = 1;
while(*MSS_CTRL_MSS_RETRAM_MEM_INIT_DONE != 1);

Regards,

Ajay

0 hu zhenguo over 3 years ago in reply to Mahmoud Russelan

Prodigy 30 points

Hi Russelan,

how to copy the vector table of the SBL,i used memcpy funcation, but it not worked.

0 Ken Zhang over 3 years ago in reply to Ajay Narayan

TI__Expert 3415 points

Hi Ajay

Why TOP_RCM::WARM_RESET_CONFIG::sw_rst not recommended to re-run SBL?

I tried it in hello_world_awr294x-evm_r5fss0-0_freertos_ti-arm-clang project ,it worked to re-run SBL.

CSL_mss_toprcmRegs* ptrTopRCMRegs = (CSL_mss_toprcmRegs*)CSL_MSS_TOPRCM_U_BASE;

CSL_FINS(ptrTopRCMRegs->WARM_RESET_CONFIG,
MSS_TOPRCM_WARM_RESET_CONFIG_WARM_RESET_CONFIG_SW_RST,
0x7U);

CSL_FINS(ptrTopRCMRegs->WARM_RESET_CONFIG,
MSS_TOPRCM_WARM_RESET_CONFIG_WARM_RESET_CONFIG_SW_RST,
0x0U);

But the same code didn't work in mmw project. Is there any restriction when using this REG in mmw demo?

0 Ajay Narayan over 3 years ago in reply to Ken Zhang

TI__Mastermind 22605 points

Hi Ken,

Sorry for the delay.

What was the issue you faced when you tried the warm reset in mmw demo?

Regards,

Ajay

0 Ken Zhang over 3 years ago in reply to Ajay Narayan

TI__Expert 3415 points

Hi Ajay

The code could re-run SBL in single core application like hello_world_awr294x-evm_r5fss0-0_freertos_ti-arm-clang while the same exact code in R5F cannot lead to a re-run of SBL in mmw demo.

Thanks

0 Jitendra Gupta over 3 years ago in reply to Ken Zhang

TI__Guru 69960 points

Hi Ken,

What I see that main difference in in these two application is presence of BSS FW image.

for the hello world binary when you flash, does it contain the BSS FW in that appImage binary file?

with BSS FW in the appImage, warm reset has a known issue for SDK 4.2 version.

Attached is the fix which is based on mmWave MCU Plus SDK 4.2.0.2

Fullscreen bootloader_soc_warm_reset_change.c Download

/* this file contains code change required for warm reset issue on AWR294x ES1.0
   below function is taken from mmWave MCU Plus SDK 4.2.0.2
   \source\drivers\bootloader\soc\awr294xbootloader_soc.c
  */
void Bootloader_socConfigurePll(void)
{
    SOC_RcmPllHsDivOutConfig hsDivCfg;
    SOC_RcmEfuseBootFreqConfig bootFreqEfuseCfg;
    int32_t retVal;
    uint32_t defaultR5Clk;

    retVal = SOC_rcmSetHSDivMux(SOC_RcmHSDIVClkOutMuxId_DPLL_CORE_OUT2,
                                SOC_RcmHSDIVClkOutMuxClockSource_DPLL_CORE_HSDIV0_CLKOUT2_PreMux);
    DebugP_assert(retVal == SystemP_SUCCESS);

    hsDivCfg.hsdivOutEnMask = (SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_1 |
                                SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_2);
    /* Configure CLKOUT1 to DSS PLL Fout/2. Divider is hsDivOut + 1 so set 1 */
    hsDivCfg.hsDivOutFreqHz[1] = SOC_RCM_FREQ_MHZ2HZ(360U);
    hsDivCfg.hsDivOutFreqHz[2] = SOC_RCM_FREQ_MHZ2HZ(240U);
    SOC_rcmDspPllConfig(SOC_RcmPllFoutFreqId_CLK_720MHZ, &hsDivCfg);
    retVal = SOC_rcmSetHSDivMux(SOC_RcmHSDIVClkOutMuxId_DPLL_DSP_OUT1,
                        SOC_RcmHSDIVClkOutMuxClockSource_DPLL_DSP_HSDIV0_CLKOUT1_PreMux);
    DebugP_assert(retVal == SystemP_SUCCESS);
    retVal = SOC_rcmSetHSDivMux(SOC_RcmHSDIVClkOutMuxId_DPLL_DSP_OUT2,
                        SOC_RcmHSDIVClkOutMuxClockSource_DPLL_DSP_HSDIV0_CLKOUT2_PreMux);
    DebugP_assert(retVal == SystemP_SUCCESS);

    hsDivCfg.hsdivOutEnMask = SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_1;
    /* Configure CLKOUT1 to DSS PLL Fout/2. Divider is hsDivOut + 1 so set 1 */
    hsDivCfg.hsDivOutFreqHz[1] = SOC_RCM_FREQ_MHZ2HZ(200U);
    SOC_rcmPerPllConfig(SOC_RcmPllFoutFreqId_CLK_1800MHZ, &hsDivCfg);
    retVal = SOC_rcmSetHSDivMux(SOC_RcmHSDIVClkOutMuxId_DPLL_PER_OUT1,
                        SOC_RcmHSDIVClkOutMuxClockSource_DPLL_PER_HSDIV0_CLKOUT1_PreMux);
    DebugP_assert(retVal == SystemP_SUCCESS);

    SOC_rcmGetEfuseBootFrequency(&bootFreqEfuseCfg);

    SOC_rcmSetR5Clock(bootFreqEfuseCfg.r5FreqHz, bootFreqEfuseCfg.sysClkFreqHz);

    SOC_rcmSetRssClkFreq(SOC_RcmRssClkSrcId_DPLL_PER_HSDIV0_CLKOUT1_MUXED, SOC_RCM_FREQ_MHZ2HZ(200U));

    /* For AWR change the UART clock to PER HSDIV CLKOUT1 insted of SYSCLK.
     * R5 clock and Sysclk is updated during boot up */
    SOC_rcmSetPeripheralClock(SOC_RcmPeripheralId_MSS_SCIA,
                              SOC_RcmPeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT1,
                              SOC_RCM_FREQ_MHZ2HZ(200U));

#if 1  //TODO JIT: change for warm reset issue
    uint32_t *reg= (uint32_t*)0x0214043C;  //MSS_TOPRCM:MSS_CR5_CLK_SRC_SEL    
    uint32_t *reg1= (uint32_t*)0x02140444;  //MSS_TOPRCM:SYS_CLK_DIV_VAL    
    *reg = 0x0;
    *reg1 = 0x0;
    
    /* CORE ADPLL reconfiguration. */
    hsDivCfg.hsdivOutEnMask = (SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_1 |
                               SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_2);
    hsDivCfg.hsDivOutFreqHz[1] = SOC_RCM_FREQ_MHZ2HZ(200U);
    hsDivCfg.hsDivOutFreqHz[2] = gCoreBootInfo[CSL_CORE_ID_R5FSS0_0].defaultClockHz;

    SOC_rcmCoreDpllConfig(SOC_RcmPllFoutFreqId_CLK_600MHZ, &hsDivCfg);
    
    *reg1 = 0x111;
    *reg = 0x222;    

#else 
    hsDivCfg.hsdivOutEnMask = (SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_0 |
                                SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_2 |
                                SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_3);
    /* RCM_PLL_HSDIV_OUTPUT_IDX0 to boot frequency R5 clock. */
    hsDivCfg.hsDivOutFreqHz[0] = bootFreqEfuseCfg.r5FreqHz;
    hsDivCfg.hsDivOutFreqHz[2] = SOC_RCM_FREQ_MHZ2HZ(240U);
    hsDivCfg.hsDivOutFreqHz[3] = SOC_RCM_FREQ_MHZ2HZ(200U);
    SOC_rcmApllHSDivConfig(SOC_RcmAPLLID_1P2G, &hsDivCfg);

    /* Change the CORE clock source to APLL 1P2G HSDIV0 CLKOUT0. */
    retVal = SOC_rcmSetHSDivMux(SOC_RcmHSDIVClkOutMuxId_DPLL_CORE_OUT2,
                        SOC_RcmHSDIVClkOutMuxClockSource_APLL_1p2G_HSDIV0_CLKOUT0);
    DebugP_assert(retVal == SystemP_SUCCESS);

    /* CORE ADPLL reconfiguration. */
    hsDivCfg.hsdivOutEnMask = (SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_1 |
                               SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_2);
    hsDivCfg.hsDivOutFreqHz[1] = SOC_RCM_FREQ_MHZ2HZ(200U);
    hsDivCfg.hsDivOutFreqHz[2] = gCoreBootInfo[CSL_CORE_ID_R5FSS0_0].defaultClockHz;

    SOC_rcmCoreDpllConfig(SOC_RcmPllFoutFreqId_CLK_600MHZ, &hsDivCfg);

    /* Change the CORE clock source back to DPLL CORE HSDIV0 CLKOUT2. */
    retVal = SOC_rcmSetHSDivMux(SOC_RcmHSDIVClkOutMuxId_DPLL_CORE_OUT2,
                                SOC_RcmHSDIVClkOutMuxClockSource_DPLL_CORE_HSDIV0_CLKOUT2_PreMux);
    DebugP_assert(retVal == SystemP_SUCCESS);
#endif
    defaultR5Clk = gCoreBootInfo[CSL_CORE_ID_R5FSS0_0].defaultClockHz;
    SOC_rcmSetR5Clock(defaultR5Clk, defaultR5Clk/2);
}

You need to merge this code change to corresponding file and rebuild the SBL tiiimage file.

Regards,

Jitendra

0 Ken Zhang over 3 years ago in reply to Jitendra Gupta

TI__Expert 3415 points

Hi Jiten

Thanks for replying! Just to confirm,

Does this warm reset issue also result in watch dog reset mode failure if BSS FW is in app on AWR2944 ES 1.0 SDK 4.2.0.3?

0 Ajay Narayan over 3 years ago in reply to Ken Zhang

TI__Mastermind 22605 points

Hi Ken,

The watch dog reset is also a type of warm reset, so any behavior of warm reset would also be applicable to watchdog reset.

Regards,

Ajay

0 Ken Zhang over 3 years ago in reply to Ajay Narayan

TI__Expert 3415 points

Thanks

I am clear now

0 Ajay Narayan over 3 years ago in reply to Ken Zhang

TI__Mastermind 22605 points

Thanks.