AWR1843: PMIC Clock out

I have written the code below to output a clock to the PMIC on pin P9. I have made several changes but cannot get any clock waveform to appear on P9. Can you please point out my mistake(s).

#define EXTCLKDIV_EXTCLK2DIV_SETTING (19)
#define EXTCLK2SRC_REFCLK ( 6)

#define DCDCCTL0_FREQUENCY_SLOPE ( 0)
#define DCDCCTL1_BITS_31_DOWNTO_2 (0x808000) //(0x8080C0)

int32_t configurePmicClock(SOC_Handle handle, int32_t* errCode)
{
SOC_DriverMCB* ptrSOCDriverMCB;
int32_t retVal = 0;

/* Get the pointer to the SOC Driver Block: */
ptrSOCDriverMCB = (SOC_DriverMCB*)handle;
if (ptrSOCDriverMCB == NULL)
{
*errCode = SOC_EINVAL;
retVal = MINUS_ONE;
}
else
{
/**********************************************************************
* Setup the PINMUX:
* Schematic signal PSU_SYNC: Configure pin P9 as PMIC_CLOCKOUT output
**********************************************************************/
Pinmux_Set_OverrideCtrl(SOC_XWR18XX_PINP9_PADBA, PINMUX_OUTPUT_EN, PINMUX_INPUT_DIS); // PINMUX_OUTEN_RETAIN_HW_CTRL, PINMUX_INPEN_RETAIN_HW_CTRL);
Pinmux_Set_FuncSel(SOC_XWR18XX_PINP9_PADBA, SOC_XWR18XX_PINP9_PADBA_PMIC_CLKOUT);

/* ===================== Setup the PMIC_CLK_GEN block. ===================== */
ptrSOCDriverMCB->ptrTopRCMRegs->DCDCCTL1 = CSL_FINSR (ptrSOCDriverMCB->ptrTopRCMRegs->DCDCCTL1,
DCDCCTL1_DCDCLKEN_BIT_END,
DCDCCTL1_DCDCLKEN_BIT_START,
(uint32_t)0);

ptrSOCDriverMCB->ptrTopRCMRegs->DCDCCTL0 = CSL_FINSR (ptrSOCDriverMCB->ptrTopRCMRegs->DCDCCTL0,
DCDCCTL0_DCDCCTL0_BIT_END,
DCDCCTL0_DCDCCTL0_BIT_START,
(uint32_t)DCDCCTL0_FREQUENCY_SLOPE);

ptrSOCDriverMCB->ptrTopRCMRegs->DCDCCTL1 = CSL_FINSR (ptrSOCDriverMCB->ptrTopRCMRegs->DCDCCTL1,
DCDCCTL1_DCDCCTL1_BIT_END,
DCDCCTL1_DCDCCTL1_BIT_START,
(uint32_t)DCDCCTL1_BITS_31_DOWNTO_2);

ptrSOCDriverMCB->ptrTopRCMRegs->DCDCCTL1 = CSL_FINSR (ptrSOCDriverMCB->ptrTopRCMRegs->DCDCCTL1,
DCDCCTL1_DCDCLKEN_BIT_END,
DCDCCTL1_DCDCLKEN_BIT_START,
(uint32_t)1);

/* ======== Setup the clock to the input of the PMIC_CLK_GEN block. ======== */
/* Gate clock */
ptrSOCDriverMCB->ptrTopRCMRegs->EXTCLKCTL = CSL_FINSR (ptrSOCDriverMCB->ptrTopRCMRegs->EXTCLKCTL,
EXTCLKCTL_EXTCLK2GATE_BIT_END,
EXTCLKCTL_EXTCLK2GATE_BIT_START,
0xADU);

/* Set clock divisor */
ptrSOCDriverMCB->ptrTopRCMRegs->EXTCLKDIV = CSL_FINSR (ptrSOCDriverMCB->ptrTopRCMRegs->EXTCLKDIV,
EXTCLKDIV_EXTCLK2DIV_BIT_END,
EXTCLKDIV_EXTCLK2DIV_BIT_START,
(uint32_t)EXTCLKDIV_EXTCLK2DIV_SETTING);

/* Set clock source */
ptrSOCDriverMCB->ptrTopRCMRegs->EXTCLKSRCSEL = CSL_FINSR (ptrSOCDriverMCB->ptrTopRCMRegs->EXTCLKSRCSEL,
EXTCLKSRCSEL_EXTCLK2SRCSEL_BIT_END,
EXTCLKSRCSEL_EXTCLK2SRCSEL_BIT_START,
(uint32_t)EXTCLK2SRC_REFCLK);

/* Ungate clock */
ptrSOCDriverMCB->ptrTopRCMRegs->EXTCLKCTL = CSL_FINSR (ptrSOCDriverMCB->ptrTopRCMRegs->EXTCLKCTL,
EXTCLKCTL_EXTCLK2GATE_BIT_END,
EXTCLKCTL_EXTCLK2GATE_BIT_START,
0U);
}
return retVal;
}