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Original question:

AMC6821 Reset I2C Hanging the Bus by Holding SDA Low

AMC6821: How to recover from latched I2C bus line

Evan Wang
Genius 9530 points
Part Number: AMC6821

Hi TI expert,

We encounter similar issue as below.

After checking the below link that it mentioned we can use 9 CLK to recover the I2C bus and the Configuration Register 4 bit 7 description.

AMC6821 Reset I2C Hanging the Bus by Holding SDA Low - Data converters forum - Data converters - TI E2E support forums

But since it is not clear so we have following questions that need your help to confirm.

1. Do you have any document that explain the function of "Configuration Register 4 bit 7" or why we have to enable this bit?

2. May we know whether we can use below method to recover the I2C bus line after it is latched?

  1. Send 10 clocks from the master to device to recover the state of SDA?
  2. Whether Host can pull low the SDA/SCL for over 30 ms in order to recover the latch of SDA?

Looking forward to your reply.

Thank you.

  • 0
    TI__Mastermind 43785 points

    Hi Chia,

    The datasheet states Register 4 Bit 7 must be 1. It's not clear why Matthew Sauceda was interested in this bit.

    Sending at least 9 clock cycles to clear the bus is a known solution for I2C. It is described in the I2C specification from NXP.

    If the data line (SDA) is stuck LOW, the controller should send nine clock pulses. The device that held the bus LOW should release it sometime within those nine clocks.

    thanks,

    ren

  • 0 in reply to Ren Schackmann
    TI__Genius 9530 points

    Hi Ren,

    Ren Schackmann said:

    The datasheet states Register 4 Bit 7 must be 1. It's not clear why Matthew Sauceda was interested in this bit.

    Yes but we would like to know why this bit has to be "1", we need more details. 

    Do you have related info can share with us?

    Ren Schackmann said:

    Sending at least 9 clock cycles to clear the bus is a known solution for I2C. It is described in the I2C specification from NXP.

    So we are not sure whether 10 clock cycle can do the same thing right?

    Evan Wang said:
    1. Whether Host can pull low the SDA/SCL for over 30 ms in order to recover the latch of SDA?

    And how about this one? will pull low the bus also help to recover from the latch status?

    Thank you.

  • 0 in reply to Evan Wang
    TI__Mastermind 43785 points

    I don't have further information to share regarding Register 4 Bit 7.

    I agree that 10 clock cycles is at least 9 clock cycles and will clear the I2C bus.

    Some devices have a 30ms time out that would recover a "latch of SDA." This time out is part of the SMBus specification. AMC6821 does not have this SMBus Timeout.

    thanks,

    ren