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AWR2944: AWR2944 spectrum spread clock SSC

Ken Zhang
Expert 3435 points
Part Number: AWR2944

Hi Experts

From the TRM of AWR2944, I see that SSC is supported by AWR2944, we could use this feature for EMI mitigation.

My questions are as follows:

(1) Does SSC have any side effect when enabled?  will it affect the RF performance?

(2) Which PLL SSC should be enabled to mitigate 1.6GHz spur? If there is no side effect, maybe we could enable SSC in all PLLs.

Thanks 

Ken 

  • +1
    TI__Guru 58035 points

    Hello Ken,

    Yes, SSC could be used to mitigate spurs caused by the clock generated by a particular ADPLL. If you spread the Core ADPLL clock, that clock is also used to generate the frame timing of the front end. So the frame timing would also be dithered with Core ADPLL SSC. If you are using clocks from other ADPLLs for any of the interfaces, spreading those clocks would dither the interface clocks as well.

    In general, we dont recommend enablling SSC by default, use it only if you are seeing an emission issue. Are you seeing a 1.6Ghz emission failure on 2944 ? That is not expected.

    regards,

    Vivek