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MMWCAS-RF-EVM: Pin-delay of CSI2 and clock signals.

Hui Chen
Intellectual 430 points
Part Number: MMWCAS-RF-EVM
Other Parts Discussed in Thread: AWR2243

Hi Ti experts,

We have started a new design based on AWR2243 cascade. Here is a question for you to confirm.

 

Since CSI2 interface is a relatively high-speed data interface, generally the entire data channel requires equal length skew between different lanes, so it is necessary to consider the routing length of these signals inside the package (i.e. pin-delay data ). How to obtain the wiring length of CSI2 and clock signals of AWR2243 in the package? Please provide the information so that we can make length compensation when routing PCB.

Thanks o lot.

Chenhui

11/05/22

  • 0
    TI__Genius 13805 points

    Hi,

        We would recommend to presume ideal load of differential interface and use s-parameters for the simulations of the trace(s) layout section only under SI analysis.

    Regards

         

  • 0 in reply to Abhed Misra
    Intellectual 430 points

    Thank you for your reply, but I think we are discussing two different things. The S parameter simulation can only evaluate the SI quality of the signal. How can we achieve the timing simulation? High speed signal timing focuses on Tset and Thold, which is related to the PCB routing length and the routing length in the package. How to evaluate it through S parameter simulation? 

    As long as pin delay is given, this can be achieved simply by setting  length matching.