IWR1642BOOST: Don't enter debug mode

Hello.

When you say you are not entering debug mode, do you mean that you are not able to connect to the cores via ccs debug?

Sincerely,

Santosh

Hi Santosh,

I can debug on CCS while the card is in functional mode. But when I do 011 (SOP Mode2) specified for debug mode in IWR1642BOOST User Guide, I cannot connect to cores. When I debug in functional mode, I encounter some problems. These are the code do not stop on breakpoints and I can not debug both cpu and dsp at the same time. Is SOP Mode2 mentioned in User Guide not used for debug? Considering the problems I mentioned while debugging, which steps should I apply? Also which bin file should be flashed in debug?

Thank you.

Hello.

Please try following this guide to make sure you are setting up the device to use ccs debug mode.  It includes a link to how to set up the hardware as well.  Let me know if this guide doesn't solve the issues you are running into.

Sincerely,

Santosh

Hi, thank you for your return.

I applied steps which in user guide and code entered loop around forever. 

If I run just Cortex_R4, I get the result like screenshot. 

And I run the core, I took result like this.

If I stopped the code, code is stopped same line because of while loop.

If I run the dsp and arm core, I took result like these "???? Could not read 0x007EA6E8: execution state prevented access [code=0x400000]".

All of these step is applied in functional mode. (I flashed ccsdebug.bin file.)

Why do I get these results? What can I do for entering debug mode correctly? 

By the way, my goal was to debug mss_main.c and dss_main.c concurrently. Is there any way to do this with these results?

Hello.

You cannot debug both cores at once.  You can only step through the MSS, but not the DSS.  This is most likely why you are running into the issues you have currently.  Also, the device should be kept in functional mode when using CCS debug; the debug SOP switch setting is for a different kind of debug.

Hope this helps,

Santosh

Hi,

Sorry for the delay. 

Is it because of the board design that I can't debug two cores at the same time? Or can both cores be debugged when a custom design is made? In the functional diagram, it is given as JTAG and UART for debug.

You said that debug SOP switch setting is for a different kind of debug. Which type of debug? Please, could you explain this?

Thank you.