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TMP121: SPI Mode 3 Support

Part Number: TMP121

Does TMP121 support SPI Mode 3?

We see in the timing diagram that SCK is shown with a "dashed" falling edge indicating that the first SCK falling edge before the first SCK rising edge is ignored. However, this is not explicitly stated in the text.

The data sheet states: "Once CS is pulled low, temperature data from the last completed conversion prior to dropping CS is latched into the shift register and clocked out at SO on the falling SCK edge."

  • Hi Peter,

    Thank you for posting to the Sensing forum and welcome to E2E!

    The data is set up on the falling edge of SCK and will be valid during the following rising edge of SCK. The dotted line in Figure 3 is meant to indicate that CS can transition while SCK is either high or low, and that SCK polarity while idle should not result in any functional differences.

    Best regards,

    Nicole

  • Hi Nicole,

    The datasheet diagram appears to show the first data bit (D15) is set up by the falling edge of CS rather than SCK even when SCK is initially high. 

    If that is not the case when SCK is initially high, is the reality more like the following two diagrams? Are t3 and t4 relative to SCK instead of CS when SCK is initially high?

    Thanks,

    Peter

  • Hi Peter,

    The datasheet diagram appears to show the first data bit (D15) is set up by the falling edge of CS rather than SCK even when SCK is initially high. 

    Yes, that is correct. The output of the TMP121 is enabled when CS goes low, regardless of the state of SCK.

    Best regards,

    Nicole

  • Please confirm the following is true:

    1. If SCK is initially high when CS goes low, the first falling edge of SCK is ignored and does not shift data.

    2. Even though you said, "that is correct", the 2nd diagram I drew in my previous message is incorrect because it shows D15 being enabled by SCK rather than CS.

    Thanks,

    Peter

  • 1. If SCK is initially high when CS goes low, the first falling edge of SCK is ignored and does not shift data.

    Correct. The state of the clock does not matter until the first rising edge.

    2. Even though you said, "that is correct", the 2nd diagram I drew in my previous message is incorrect because it shows D15 being enabled by SCK rather than CS.

    Yes, your first statement regarding the data bit being set up by the falling edge of CS instead of SCK was correct. The second diagram you attached is incorrect, because the state of SCK before the first rising edge doesn't affect data shifting.

    Best regards,
    Nicole