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IWR1642: IWR1642 Power-on Sequence Consultation

user5883945
Expert 1826 points
Part Number: IWR1642
Other Parts Discussed in Thread: IWR6843,

Dears,

    Customer have some question about power-on Sequence,

     

    1. As shown in Figure 1 of the power-on sequence diagram in the chip datasheet, it takes 3ms for the chip to be powered on and reset. Does the power-on reset time refer to the time from VIOIN(3.3V) to NRESET          VIH(3.3V Mode)1.57V(Figure 2)? As shown in the following figure

2. When the IC starts, whether there is any requirement on the power-on climbing time (0V to 3.3V stable) of VIOIN(3.3V stable)

3. The chip starts. Do the VIOIN (3.3V), VIOIN_18DIFF (1.8V), VDDIN (1.2V), VIN* (1.8V, LDO1V) multicircuit power supplies shown in Figure 1 have time sequence requirements?

4. If the chip is in flash startup mode, is there any requirement on the POWER failure time sequence (POWER DOWN 3ms marked on the right side of Figure 1)?

5. Some products sometimes start 350mS slowly (the comparison between the two products), what is the cause?

     It is confirmed that there are differences in flash data: (the yellow channel at the top is abnormal products, while the green channel at the bottom is normal products)

     

the SCLK clock had intermittent phenomenon, and the difference was about 350ms, which was basically consistent.

  • 0
    Expert 1826 points

    Dears，

        Do you have any upstate, thanks!

  • 0 in reply to user5883945
    TI__Mastermind 25835 points

    Hello user5883945,

    Please find the response to above comments 

    1)  Power up time from the VIO to NRESET release is shown is approximately 3msec, This is mainly to ensure all the supply including VIO need to be stable before NRESET release.  If NRESET release happens prior to VIO and other supplies then there is possibility of wrong SOP mode detection, Hence guidance of NRESET release 3msec after the supplies are stable is shown. 3msec is not a hard requirement but need to be released after all the power supplies are stable. 

    2) There is no requirement for the power up climbing typically it depends upon the power delivery network output impedance and amount of decoupling caps on the board. 

    3) & 4) There is no supply sequencing requirements for power up and power down scenario. 

    5) It is possible that NRESET release have different time constant in different product and that might cause difference in timing. Also some products have different QSPI clock frequency i.e. for example IWR1642 devices operates at 40MHz where as IWR6843 device operates at 80MHz. Also application code size also vary from product to product causing boot time to change from product to product. 

    Thanks and regards,

    CHETHAN KUMAR Y.B. 

  • 0 in reply to CHETHAN KUMAR Y.B.
    TI__Genius 9320 points

    Hi Chethan,

    this issue is reported from my customer. They found the issue on about 10% percentage IWR1642 modules. Here would like to know in which case would reduce the QSPI clock from 40MHZ to 8MHZ?

    Andy

  • 0 in reply to Andy Yin
    TI__Mastermind 25835 points

    Andy,

        During the power up reading from the QSPI flash happens from ROM at 80MHz, At that point in time there is no flexibility to change the frequency of the QSPI, After the boot up frequency could be changed to much lower frequency.

    During startup, It's important to have clean bandgap reference for the device, that needs good 47nF cap as shown below, Otherwise there could be startup issues. Could you please confirm you have below cap on the Bandgap pin. 

    Also, Is it possible to review the schematic of the design? 

    Thanks and regards,

    CHETHAN KUMAR Y.B.

  • 0 in reply to CHETHAN KUMAR Y.B.
    TI__Genius 9320 points

    Hi Chethan,

    The issue is found on IWR1642, while i don't find the bandgap problem in IWR1642 errata. 

    And once customer reported the above issue the only impact is that the boot time is longer(plus 350ms, then find the QSPI clock is decreased to 8MHZ), while it still can boot up well and doesn't have other issue.

    Andy

  • 0 in reply to Andy Yin
    TI__Mastermind 25835 points

    Andy,

        Reference design for IWR1642 also changed due to this issue, Earlier in Rev B version of the reference design bandgap capacitor was 220nf, and later in Rev C version this is revised to 47nF with the above recommended part. 

    Below is the note in the schematic package:

    Do you have the schematic of the design? 

    Thanks and regards,

    CHETHAN KUMAR Y.B.

  • 0 in reply to CHETHAN KUMAR Y.B.
    Expert 1826 points

    Hi Chethan,

       Does the 1843 and 6843 have same issue, thanks!

  • 0 in reply to user5883945
    TI__Mastermind 25835 points

    Andy,

        If you use 220nF cap on the bandgap in, It will have same issues, Hence recommended to change to 47nF (GRM155R71E473KA88) capacitor. 

    Thanks and regards,

    CHETHAN KUMAR Y.B.