Hello,
we are doing some tests to boot 4 AWR2243P in our own design but unsucessfully for now (radar chips do not send anything on MISO SPI).
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Question 1 : if QSPI flash is present but with nothing stored in memory, will the AWR2243, I understand that the chip will automatically fall back into the SPI bootmode, is that correct ?
We probed the signals (Master chip) of an automotive radar from which we want to use the host firmware :
We see that immediatly after NRESET goes high, SPI INT rises and we can see communications on SPI MISO and MOSI.
Now, here is we measure the signals on an own design :
First difference with the automotive reference design : the level of the two first rises is high and not intermediate. We notice that SPI INT goes high for a very short time with the 2 first NRESET rises, but remains low on the third NRESET, which is the "real" start signal of the chip.
Question 2 : What is the condition for the SPI INT to go high when NRESET is pulled up ?
Question 3 : do you have any advices on what signals we should probe in order to know if AWR2243 chip is correctly going through boot sequence ?
Thanks.
Best regards.
Jeff


