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AWR6843AOP: AWR6843ISK RTI free-running counter

Cherry Zhou
Mastermind 22235 points
Part Number: AWR6843AOP
Other Parts Discussed in Thread: AWR6843

Hi Team,

Here's an issue from the customer may need your help:

The question is based on the following two premises:

A. Free running counter 0/1 is an overflow interrupt generated when UC0/1 = RTICUC0/1 accumulates 1 and when the count reaches the 0xffff_ffff boundary.

B. Also, a compare int0/1/2/3 interrupt is generated when Free running counter 0/1 = RTICOM0/1.

Issues:

1) An overflow interrupt is an exception, so to avoid an overflow interrupt, is it required to clear Free running counter 0/1 when a compare interrupt occurs?

However, the customer did not find the correspond code in the SDK and the declaration RTIFRC1_FRC0/1_bit_end in the .h file was not referenced.

2) Given some differences in interrupt response times, how to make sure the timer outputs exactly as set if the under the above case?

3) If the Free running counter 0/1 is not cleared by a compare interrupt, the overflow interrupt is generated periodically, is it normal? And in this case, how to generate a compare int0/1/2/3 with different timestamp information? (since the count period for Free running counter 0/1 is fixed at this time)

Could you please help look into this case? Thanks.

Best Regards,

Cherry

  • 0
    TI__Expert 3525 points

    Hi Cherry,

    We will look into this and update next week.

    Best Regards,
    Kevin 

  • 0 in reply to Kevin Ortiz
    TI__Mastermind 22235 points

    Hi Kevin,

    Thanks for your support and expect the response.

    Regards,

    Cherry

  • 0
    TI__Expert 3525 points

    Hi Cherry,

    Apologies for the delay. Please see responses below

    1) The free running counter will increment by one everytime UC and COMP valuse match. As the FRC reaches 0xFFFFFFFF it needs to be cleared in order to get the next overflow interrupt to occur.

    2) A good option here is to set RTI interrupt priority as the highest priority relative to the other interrupts. In RTI ISR, clear the interrupt as the first step. 

    3) Overflow interrupt would be generated until the max value of 0xFFFFFFFF is reached. The user needs to configure the below registers to enable int0/1/2/3 events:

    RTIUDCP0

    RTICOMP1

    RTIUDCP1

    RTICOMP2

    RTIUDCP2

    RTICOMP3

    RTIUDCP3

    Best Regards,
    Kevin 

  • 0 in reply to Kevin Ortiz
    TI__Mastermind 22235 points

    Hi Kevin,

    Thanks for the response. The case here is what is the count boundary value for free running counter? 

    Based on the above response, the free running counter sure to count to 0xffff_ffff, right? That is, an overflow interrupt must occur.

    If the free running counter has a fixed count range of 0x0000_0000 - 0xffff_ffff, assuming RTICOMP0=0XF, RTICOMP1=0XFF, and COMPSEL0=0, COMPSEL1 = 0, then the interrupt cycles for compare int0 and compare INT1 are the same, except that the compare int0 interrupt occurs earlier. And compare int0 and compare INT1 adjacent interrupts have the same time span. If this is the case, the following configuration is not possible to implement:

    OR if we could say that there are actually 4 free-running counters inside the AWR6843 instead of the 2 mentioned in the document.

    The count boundary for free-running counter0 is RTICOMP0, and the count boundary for free-running counter1 is RTICOMP1. The count boundary for free-running counter3 is RTICMP2, and the count boundary for free-running counter3 is RTICOMP3.

    If this is the case, then different compare int cycles can be implemented, and the above can be implemented.

    Thanks and Regards,

    Cherry

  • 0 in reply to Cherry Zhou
    TI__Expert 3525 points

    Hi Cherry,

    We are going to have to do a little deeper digging internally with our experts on this. Please give us until early next week to respond.

    Thank you,
    Kevin

  • 0 in reply to Kevin Ortiz
    TI__Mastermind 22235 points

    Hi Kevin,

    Thanks and expect the updates.

    Best,

    Cherry

  • 0
    TI__Expert 3525 points

    Hi Cherry, 

    Sorry for the delay.

    As per below screenshot, if both “MSS_RTIA compare interrupt 0” and “MSS_RTIA compare interrupt 1” interrupts are enabled and both interrupts occur at the same time then “MSS_RTIA compare interrupt 0” interrupt is prioritized over “MSS_RTIA compare interrupt 1” ( This is based on the lowest interrupt channel number)

    Best Regards,

    Kevin