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IWR6843: L3 memory coherence - is it required when not using DPM ?

Maximilien B
Prodigy 115 points
Part Number: IWR6843

In the DPM library, I understand the mailbox hardware / driver takes care of synchronization events between MSS / DSS domains and sending small messages.

However, as far as shared memory is concerned, the bulk of the data does not go trough mailbox memory, it is directly read / written on L3 shared memory. This requires cache coherence operations when using L1/L2 cache on DSS and I can't find any reference to cache coherence operations in the DPM documentation or code.

For example, when generating detected points back for MSS, in theory the points should be written to L1/L2 cache, and may never be written back to L3 to be available to MSS.

Is any cache coherence operation made at any point that I missed ? If not, why is it not required ?

The goal is to explore the possibility of using the device without DPM library's rigid flow.

  • 0
    TI__Expert 4448 points

    Hello,

    Allow me to look into this internally for you. You can expect a response within 48 hours.

    Regards,

    Luke

  • +1 in reply to Luke Rouleau
    TI__Expert 4448 points

    The DSP is not cache-coherent with the L3 memory, so on the SDP side, we have two data transfer directions. The rule is this:

    • DSP  writing data to L3 memory that would be picked up by ARM or EDMA: In this case, always after writing data to L3, we would call cache write back API (with arguments, pointer to data, and data length, and then we would trigger EDMA or send message to ARM.
    • DSP reading data from L3 memory that was written from ARM or EDMA: In this case, always before reading data, we would call cache invalidate API with arguments: pointer to data, and data size.

    In the People Counting Demo we called cache invalidate only once per frame and for all cache. This was done because DSP, while processing L3 data, was reading and writing it back, and later this memory would be populated with the new frame data, and we wanted to have clean cache for the next frame processing, since the DSP could randomly overwrite old (from previous) data to L3 over the new fresh data.

    Regards,

    Luke

  • 0 in reply to Luke Rouleau
    Prodigy 115 points

    Indeed the writeback/invalidate is done in the demo and not as part of the DPM library ! I have found the reference in the demo's dpmTask function.

    Thank you so much for your response.

    Maximilien