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Original question:

IWR6843AOP: max SPI sample rade

IWR6843AOP: SPI sampling rate range, regulation method

Deca YJ SU
Prodigy 75 points
Part Number: IWR6843AOP

A. SPI Sample Rate Range

In the DATASHEET, you can know that the system clock is 40MHz no matter it is generated internally or an external oscillator is installed.

And SPICLK is adopted in two modes from the document:
1) Controller mode: SPICLK is generated inside the IC.
2) Peripheral mode: SPICLK is received by external clock source input.

[Q] What is the SPI sampling rate range of these two modes?
[A]*The following is the current understanding, please help to correct any mistakes.

1) Controller mode:
Range => ?? Hz[=1/256tc(VCLK)] ~ 40MHz[=1/25ns]
*What is the parameter [tc(VCLK)]?

2) Peripheral mode: determined by the external clock source input, the maximum is 40MHz[=1/25ns].
Range => 0 ~ 40MHz[=1/25ns]

B. Sampling rate Control method
[Q] How to control the sampling rate of the two modes of SPI?

  • +1
    TI__Mastermind 37780 points
    Deca YJ SU said:

    *What is the parameter [tc(VCLK)]?

    I think there is a typo in this table. I would be willing to bet that 256tc(VCLK) should be 256tc(VCLK), in which case it is covered by (2), below the table, which reads:

    The main subsystem clock time can be selected as shown in the TRM.

    Deca YJ SU said:
    [Q] How to control the sampling rate of the two modes of SPI?

    If you're in central mode, then you control the baud rate through the SPI_MasterModeParams_t structure called in SPI_init(). See the Doxygen for more detail found at this location : C:/ti/mmwave_sdk_03_06_00_00-LTS/packages/ti/drivers/spi/docs/doxygen/html/index.html

    Best

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