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TMP100: hold up time

Part Number: TMP100

Hi Team,

Why does  this device define max time of data hold time?

My customer mentioned It's too short bcz if SCL 100kHz, data hold time  might be 4000n~5000n.

This device doesn't work in I2C Standard-mode? What is min value of SCL frequency?



  • Dear Shoo - 

    The fast mode column is intended to cover standard and fast mode. The max hold time is defined to meet the note in the I2C spec (page 44 of the 2021 version of the spec) for Thd,dat, which reads: 

    [3] The maximum tHD;DAT could be 3.45 μs and 0.9 μs for Standard-mode and Fast-mode, but must be less than the maximum of tVD;DAT or tVD;ACK by a transition time. This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.

    The TMP100 has no issues at 100kHz I2C clock speed.