This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AWR2944: HWA FFT required clock cycle

Part Number: AWR2944

Hi

I have some questions about HWA 2.0.

Because I would like to confirm that the HWA have been achirving maximum peformance for FFT, I compared the actually required clock cycles with the theoretically estimated clock cycles.

Regarding the actually required clock cycles, 
I confirmed the clock cycles using the Real FFT program that mmwave mcuplus SDK provids.

Regarding the theoretically estimated clock cycles,
I confirmed the HWA user guide part of AWR294x Technical Reference Manual.
Addtionally, I estimated clock cycle required HWA FFT refer to the HWA user guide (below image).

The result are as follows.

**********************************************************************************************

number of FFT sample / Actual clock cycles / Estimated clock cycles per once FFT

256 / 2467 / 512( =256+ (256x1) )

512 / 3101 / 1024

1024 / 4041 / 2048

**********************************************************************************************

1) How accurate is the estimation value of clock cycle refer to HWA user guide?

2) What the reason do you think about that difference between the clock cycle I confirmed using AWR2944 and estimated clock cycle refer to AWR294x Technical Reference Manual occurred?

Regards,

Naoya

  • Hi Naoya,

    1. It is the exact number of cycles taken by the HWA on silicon.
    2. The difference is caused because of additional overheads of interrupts & EDMA, static latencies, OS overheads etc (Based on how you have timed the param executions). This difference would typically be a very small value and usually will be constant almost.

    Regards,

    Kaushik