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IWR1843: The power supply ripple noise gets worse

Part Number: IWR1843

Hi team,

The customer have developed custom board using the IWR1843 chip scheme. The power supply is designed based on reference documentation and development boards. The 1V/1.24V/1.8V/3.3V rails powering the 1843 were subjected to similar modulated signals during the test, causing the power supply ripple noise to worsen. A similar behavior was observed when testing the IWR1843BOOST development board. How can the impact of this noise be assessed? Does this interference have to be eliminated? 

The ripple noise waveform is tested using the 1.24-V rail as an example: 

Away from 1843: 

Close to 1843: 

Amplify the modulated glitch waveform: 

And could you help review the design?

https://e2echina.ti.com/cfs-file/__key/communityserver-discussions-components-files/118/3187.1843_5F00_afe.pdf

Could you help check this case? Thanks.

Best Regards,

Cherry

  • Hi Cherry,

    I have forwarded this to the correct member of our team. Can you let us know who the customer is?

    Regards,

    Tim

  • Hi Cherry,

    We will need to review the schematic design. Although it could take some time, we will reply to you soon.

    Regards

    Ankit

  • Hi Cherry,

    The ripple may be due to incorrect LC filter combinations.

    There are some improvements that can be done on the radar schematics.

    • In 'IWR1843' schematic section, please use 4.7pF cap instead of 5.6pF in XTAL.
    • Use 0.047uF decap for VBGAP instead of 0.22uF.
    • In 'Power" schematic section, the ferrite bead between C39 and C40 is missing, also please use 4.7uF & 47uF caps instead of 22uF & 0.1uF (C39 & C40).
    • 22uF caps for C43,44,45 & 0.1uF for C42 & 4.7uF cap for C41 is recommended.
    • 10kOhm pull up is recommended from Warmreset to 3.3V instead of direct connection.
    • Add 10uF cap in parallel to C51,52
    • 47uF,10uF,10uF in parallel instead of C53
    • In LC filters, caps were missing for 1.23,3.3 & 1V. 10uF,22uF cap in parallel is recommended.
    • In SOP switch, SOP signals are absent. Please follow below reference if they intend to use the SOP modes.

    Rest of the schematic sections are correct. The above-mentioned L, C values are the recommended values as per IWR1843 EVM reference schematic.

    Regards

    Ankit