AWR2944EVM: Issue with the mmWave Studio

Daisuke Maeda

Guru 20205 points

Part Number: AWR2944EVM
Other Parts Discussed in Thread: DCA1000EVM, AWR2944

Our customer wants to use AWR2944EVM and DCA1000EVM to get ADC data with 4TX and 4RX. In particular, they want to make a MIMO measurement that switches every single Tx.
They were able to get the data using the mmWave Studio 3.1.1, but the Chirp Manager cannot be activated with an error, so they don't know if the Tx is switched.

The settings in the mmWave Studio 3.1.1 are summarized below. The default values are used for all settings except as noted.

1. The firmware is located at the following location (C:\ti\mmwave_studio_03_01_01_00\rf_eval_firmware\AWR2944_ES2)

2. In the StaticConfig tab, under "Static Configuration"-"Basic Configuration"-"Channel Config", add checks for Tx2 and Tx3.

3. In the DataConfig tab, under "LVDS Lane Configuration"-"Lane Config", add a check for Lane 2.

4. In the SensorConfig tab, under "Sensor Configuration"-"Chirp"-"TX Enable for current chirp", add checks for TX2 and TX3 and set "End Chirp for Cfg" to 3.

5. In the SensorConfig tab, under "Sensor Configuration"-"Frame", set "End Chirp TX" to 3 and "No of Chirp Loops" to 60.

Could you tell me the necessary settings?

Best regards,

Daisuke

over 2 years ago

0 Daisuke Maeda over 2 years ago

Guru 20205 points

Hi,

Add the captured Chirp Manager image.

Best regards,

Daisuke

0 Saswat Kumar over 2 years ago in reply to Daisuke Maeda

TI__Mastermind 35715 points

Hello Daisuke,

Let me analyze and get back with a response by Tuesday.

Regards,
Saswat Kumar

0 Daisuke Maeda over 2 years ago in reply to Saswat Kumar

Guru 20205 points

Hi Saswat-san,

Thank you for your support. Our customer is waiting for your response.

Please give me an answer as soon as possible. Your prompt reply would be appreciated.

Best regards,

Daisuke

0 Saswat Kumar over 2 years ago in reply to Daisuke Maeda

TI__Mastermind 35715 points

Hello Daisuke-san,

Could you please provide the lua script which has the commands being invoked and chirping diagram, so we can reproduce the same on our end and check.

Regards,
Saswat Kumar

0 Daisuke Maeda over 2 years ago in reply to Saswat Kumar

Guru 20205 points

Hi Saswat-san,

Thank you for your reply.

Our customer does not use the lua script which has the commands being invoked and chirping diagram.

The mmWave Studio 3.1.1 only includes the script "Startup.lua" that runs when the GUI starts up, and the scripts in the Startup folder that run together.

C:\ti\mmwave_studio_03_01_01_00\mmWaveStudio\Scripts\
Startup\
BinDecHex.lua
General_functions.lua
lib_math.lua
Startup.lua

Could you provide a script to test it?

Best regards,

Daisuke

0 Saswat Kumar over 2 years ago in reply to Daisuke Maeda

TI__Mastermind 35715 points

Hello Daisuke,

When you execute these commands, you can also observe that in the output window, the functions are being invoked. These commands are used in the lua script.
So, can you ask the customer to make one and share the same?

Regards,
Saswat Kumar

0 Daisuke Maeda over 2 years ago in reply to Saswat Kumar

Guru 20205 points

Hi Saswat-san,

Thank you for your reply.

Should the log file be shared to check the log in the output window?

The log file can be checked from "Show Log File" in the right-click menu in the output window.

Best regards,

Daisuke

0 Saswat Kumar over 2 years ago in reply to Daisuke Maeda

TI__Mastermind 35715 points

Hello Daisuke,

You can share it once and we can try to extract it out of it. Let me check it with the team after that.

Regards,

Saswat Kumar

0 Daisuke Maeda over 2 years ago in reply to Saswat Kumar

Guru 20205 points

Hi Saswat-san,

Thank you for your reply.

Attach the file with the log in the output window.

Fullscreen 0447.output_window_log.txt Download

GM: Constructor
GM: Wed Aug 16 15:27:49 2023
RSTD.Transmit("/Settings")
[15:27:49]  
[15:27:49]  ### Running Startup script: "C:\ti\mmwave_studio_03_01_01_00\mmWaveStudio\Scripts\Startup.lua" ###
[15:27:49]  RSTD.SetAndTransmit ("/Settings/Scripter/Display DateTime" , "1")
[15:27:49]  RSTD.SetAndTransmit ("/Settings/Scripter/DateTime Format" , "HH:mm:ss")
[15:27:49]  Scripter ignored: Attempt to UnBuild() again or before Build.
[15:27:49]  RSTD.SetVar ("/Settings/Clients/Client 0/Dll" , "C:\\ti\\mmwave_studio_03_01_01_00\\mmWaveStudio\\Clients\\\\LabClient.dll")
[15:27:49]  RSTD.SetVar ("/Settings/Clients/Client 0/Use" , "TRUE")
[15:27:49]  RSTD.SetVar ("/Settings/Clients/Client 1/Use" , "FALSE")
[15:27:49]  RSTD.SetVar ("/Settings/Clients/Client 2/Use" , "FALSE")
[15:27:49]  RSTD.SetVar ("/Settings/Clients/Client 3/Use" , "FALSE")
[15:27:50]  RSTD.SetVar ("/Settings/Clients/Client 4/Use" , "FALSE")
[15:27:50]  RSTD.SetVar ("/Settings/AL Client/AL Dll" , "C:\\ti\\mmwave_studio_03_01_01_00\\mmWaveStudio\\RunTime\\SAL.dll")
[15:27:50]  RSTD.SetVar ("/Settings/Clients/Client 0/GuiDll" , "")
[15:27:50]  RSTD.SetVar ("/Settings/AutoUpdate/Enabled" , "TRUE")
[15:27:50]  RSTD.SetVar ("/Settings/AutoUpdate/Interval" , "1")
[15:27:50]  RSTD.SetVar ("/Settings/Monitors/UpdateDisplay" , "TRUE")
[15:27:50]  RSTD.SetVar ("/Settings/Monitors/OneClickStart" , "TRUE")
[15:27:50]  RSTD.SetVar ("/Settings/Automation/Automation Mode" , "false")
[15:27:50]  RSTD.Transmit("/")
[15:27:50]  RSTD.SaveSettings(): Settings saved to "C:\Users\254300\AppData\Roaming\RSTD\config.xml"
[15:27:50]  RSTD.Build()
[15:27:50]  RSTD.SaveSettings(): Settings saved to "C:\Users\254300\AppData\Roaming\RSTD\config.xml"
[15:27:50]  RSTD.Transmit("/")
[15:27:50]  RSTD.AL_Build()
[15:27:50]  RSTD.AL_LoadXml()
[15:27:50]  RSTD.Transmit("/")
[15:27:50]  RSTD.AL_Init()
[15:27:50]  RSTD.Clients_Build()
[15:27:50]  GM: Init
[15:27:50]  GM: Loaded 'C:\ti\mmwave_studio_03_01_01_00\mmWaveStudio\Clients\\LabClient.dll'
[15:27:50]  GM: 1 Guest (s) init
[15:27:50]  GM: 1 Module(s) init
[15:27:50]  GM: 2 Tab   (s) init
[15:27:50]  RSTD.Client_LoadXml()
[15:27:50]  [RadarAPI]: ar1.GuiVersion()
[15:27:50]  [RadarAPI]: ar1.selectRadarMode(0)
[15:27:50]  [RadarAPI]: Status: Passed
[15:27:50]  Matlab Runtime Engine is installed
[15:27:50]  [RadarAPI]: Starting Matlab Engine..
[15:27:53]  [RadarAPI]: Matlab Engine Started!
[15:27:56]  [RadarAPI]: ar1.selectCascadeMode(0)
[15:27:56]  [RadarAPI]: Status: Passed
[15:27:56]  [RadarAPI]: ar1.LoadSettings('C:\Users\254300\AppData\Roaming\RSTD\ar1gui.ini')
[15:27:57]  TESTING = false
[15:27:57]  RstdNet: Port 2777: Listening..
[15:27:57]  
[15:27:57]  ***Script completed successfully.***
[15:30:55]  [RadarAPI]: Opening Gpio Control Port()
[15:30:55]  [RadarAPI]: Status: Passed
[15:30:56]  [RadarAPI]: Opening Board Control Port()
[15:30:56]  [RadarAPI]: Status: Passed
[15:30:57]  [RadarAPI]: ar1.FullReset()
[15:30:57]  [RadarAPI]: Status: Passed
[15:30:58]  [RadarAPI]: Closing Board Control Port()
[15:30:58]  [RadarAPI]: Status: Passed
[15:30:58]  [RadarAPI]: Closing Gpio Control Port()
[15:30:58]  [RadarAPI]: Status: Passed
[15:30:58]  [RadarAPI]: ar1.SOPControl(2)
[15:30:58]  [RadarAPI]: Status: Passed
[15:31:04]  [RadarAPI]: ar1.Connect(19,921600,1000)
[15:31:07]  [RadarAPI]: Warning: Connected with baudrate 115200
[15:31:08]  [RadarAPI]: Warning: Disconnected existing BaudRate
[15:31:08]  [RadarAPI]: Warning: Trying to connect with baudrate 921600
[15:31:10]  [RadarAPI]: ar1.Calling_IsConnected()
[15:31:11]  [RadarAPI]: Part number of the device = 0x98
[15:31:11]  [RadarAPI]: Device type = GP
[15:31:11]  [RadarAPI]: ar1.SelectChipVersion("AR1642")
[15:31:11]  [RadarAPI]: Status: Passed
[15:31:11]  [RadarAPI]: ar1.deviceVariantSelection("XWR2944")
[15:31:11]  [RadarAPI]: Status: Passed
[15:31:11]  [RadarAPI]: ar1.frequencyBandSelection("77G")
[15:31:11]  [RadarAPI]: ar1.SelectChipVersion("AWR2944")
[15:31:11]  [RadarAPI]: Status: Passed
[15:31:11]  Device Status : AWR2944/GP/ASIL-B/SOP:2/ES:2.0
[15:31:11]  [RadarAPI]: ar1.SaveSettings('C:\Users\254300\AppData\Roaming\RSTD\ar1gui.ini')
[15:31:38]  [RadarAPI]: ar1.DownloadBSSFw("C:\\ti\\mmwave_studio_03_01_01_00\\rf_eval_firmware\\AWR2944_ES2\\radarss\\xwr29xx_radarss.bin")
[15:31:42]  [RadarAPI]: ar1.GetBSSFwVersion()
[15:31:42]  [RadarAPI]: BSSFwVersion:(02.04.05.03 (20/04/22))
[15:31:43]  [RadarAPI]: ar1.GetBSSPatchFwVersion()
[15:31:43]  [RadarAPI]: BSSPatchFwVersion:(02.04.08.03 (24/03/23))
[15:31:44]  [RadarAPI]: ar1.DownloadMSSFw("C:\\ti\\mmwave_studio_03_01_01_00\\rf_eval_firmware\\AWR2944_ES2\\masterss\\xwr29xx_masterss.bin")
[15:31:47]  [RadarAPI]: Downloading MSS RPRC Binary..
[15:31:51]  [RadarAPI]: ar1.GetMSSFwVersion()
[15:31:51]  [RadarAPI]: MSSFwVersion:(02.04.01.07 (15/02/23))
[15:31:55]  [RadarAPI]: ar1.PowerOn(0, 1000, 0, 0)
[15:31:55]  [RadarAPI]: Status: Passed
[15:31:55]  MSS power up done async event received!
[15:31:57]  [RadarAPI]: ar1.RfEnable()
[15:31:57]  BSS power up done async event received!
[15:31:57]  [RadarAPI]: Status: Passed
[15:31:57]  [RadarAPI]: ar1.GetMSSFwVersion()
[15:31:57]  [RadarAPI]: MSSFwVersion:(02.04.01.07 (15/02/23))
[15:31:58]  [RadarAPI]: ar1.GetBSSFwVersion()
[15:31:58]  [RadarAPI]: BSSFwVersion:(02.04.05.03 (20/04/22))
[15:31:59]  [RadarAPI]: ar1.GetBSSPatchFwVersion()
[15:31:59]  [RadarAPI]: BSSPatchFwVersion:(02.04.08.03 (24/03/23))
[15:32:12]  [RadarAPI]: ar1.ChanNAdcConfig(1, 1, 1, 1, 1, 1, 1, 1, 2, 0, 0)
[15:32:13]  [RadarAPI]: Status: Passed
[15:32:15]  [RadarAPI]: ar1.LPModConfig(0, 0)
[15:32:15]  [RadarAPI]: Status: Passed
[15:32:16]  [RadarAPI]: ar1.RfInit()
[15:32:16]  RF Init async event received!
[15:32:17]  [RadarAPI]: Time stamp, Temperture: 19739,38; SynthVCO3 Status, Update: 0, 0; APLL Status, Update: 1, 0; SynthVCO1 Status, Update: 1, 1; SynthVCO2 Status, Update: 1, 1; LODist Status, Update: 1, 1; RxADCDC Status, Update: 1, 1; HPFcutoff Status, Update: 1, 1; LPFcutoff Status, Update: 1, 1; PeakDetector Status, Update: 1, 1; TxPower Status, Update: 1, 1; RxGain Status, Update: 1, 1; TxPhase Status, Update: 1, 1; RxIQMM Status, Update: 0, 0; 
[15:32:17]  [RadarAPI]: Status: Passed
[15:32:28]  [RadarAPI]: ar1.DataPathConfig(513, 1216644097, 0)
[15:32:28]  [RadarAPI]: Status: Passed
[15:32:31]  [RadarAPI]: ar1.LvdsClkConfig(1, 1)
[15:32:31]  [RadarAPI]: Status: Passed
[15:32:33]  [RadarAPI]: ar1.LVDSLaneConfig(0, 1, 1, 0, 0, 1, 0, 0)
[15:32:33]  [RadarAPI]: Status: Passed
[15:34:02]  [RadarAPI]: ar1.ProfileConfig(0, 77, 100, 6, 60, 0, 0, 0, 0, 0, 0, 0, 0, 29.982, 0, 256, 10000, 2216755200, 0, 30, 0, 0, 0)
[15:34:02]  [RadarAPI]: Status: Passed
[15:34:23]  [RadarAPI]: ar1.ChirpConfig(0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0)
[15:34:23]  [RadarAPI]: Status: Passed
[15:34:30]  [RadarAPI]: ar1.ChirpConfig(1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0)
[15:34:30]  [RadarAPI]: Status: Passed
[15:34:36]  [RadarAPI]: ar1.ChirpConfig(2, 2, 0, 0, 0, 0, 0, 0, 0, 1, 0)
[15:34:36]  [RadarAPI]: Status: Passed
[15:34:41]  [RadarAPI]: ar1.ChirpConfig(3, 3, 0, 0, 0, 0, 0, 0, 0, 0, 1)
[15:34:41]  [RadarAPI]: Status: Passed
[15:35:53]  Test Source Already Disabled...!!!
[15:35:53]  [RadarAPI]: ar1.DisableTestSource(0)
[15:35:53]  [RadarAPI]: Status: Passed
[15:35:53]  [RadarAPI]: ar1.FrameConfig(0, 3, 8, 60, 40, 0, 1)
[15:35:53]  [RadarAPI]: Status: Passed
[15:36:52]  [RadarAPI]: ar1.GetCaptureCardDllVersion()
[15:36:52]  [RadarAPI]: Sending dll_version command to DCA1000
[15:36:52]  [RadarAPI]: 
[15:36:52]  DLL Version : 1.0
[15:36:52]  [RadarAPI]: ar1.SelectCaptureDevice("DCA1000")
[15:36:52]  [RadarAPI]: Status: Passed
[15:36:54]  [RadarAPI]: ar1.CaptureCardConfig_EthInit("192.168.33.30", "192.168.33.180", "12:34:56:78:90:12", 4096, 4098)
[15:36:54]  [RadarAPI]: ar1.CaptureCardConfig_Mode(1, 2, 1, 2, 3, 30)
[15:36:54]  [RadarAPI]: ar1.CaptureCardConfig_PacketDelay(25)
[15:36:54]  [RadarAPI]: Sending fpga command to DCA1000
[15:36:55]  [RadarAPI]: 
[15:36:55]  FPGA Configuration command : Success
[15:36:55]  [RadarAPI]: Sending record command to DCA1000
[15:36:55]  [RadarAPI]: 
[15:36:55]  Configure Record command : Success
[15:36:55]  [RadarAPI]: ar1.GetCaptureCardFPGAVersion()
[15:36:55]  [RadarAPI]: Sending fpga_version command to DCA1000
[15:36:55]  [RadarAPI]: 
[15:36:55]  
[15:36:55]  FPGA Version : 2.9 [Record]
[15:36:55]  
[15:37:19]  [RadarAPI]: ar1.CaptureCardConfig_StartRecord("C:\\ti\\mmwave_studio_03_01_01_00\\mmWaveStudio\\PostProc\\adc_data.bin", 1)
[15:37:19]  [RadarAPI]: Sending start_record command to DCA1000
[15:37:22]  [RadarAPI]: ar1.StartFrame()
[15:37:22]  [RadarAPI]: Status: Passed
[15:37:22]  Frame start async event received!
[15:37:23]  [RadarAPI]: Frame Ended
[15:37:25]  [RadarAPI]: 
[15:37:25]  Frame End async event received!
[15:37:25]  [RadarAPI]: 
[15:37:25]  Start Record command : Success
[15:37:25]  
[15:37:25]  Record is completed
[15:37:25]  
[15:37:25]  Record stop is done successfully
[15:37:36]  [RadarAPI]: ar1.StartMatlabPostProc("C:\\ti\\mmwave_studio_03_01_01_00\\mmWaveStudio\\PostProc\\adc_data.bin")
[15:37:36]  [RadarAPI]: No of files Captured: 1, Total no of frames for each device : 8
[15:42:48]  Provide the path and filename for the Export of Capture Setup JSON configuration.
[15:42:53]  Provide the path and filename for the Export of mmWave JSON configuration.
[15:42:56]  Export Operation was successful!
[16:20:30]  [RadarAPI]: ar1.ChirpConfig(3, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0)
[16:20:31]  [RadarAPI]: Status: Passed
[16:20:58]  [RadarAPI]: ar1.CaptureCard_DisConnect()
[16:20:58]  [RadarAPI]: Status:Passed
[16:20:59]  [RadarAPI]: ar1.CaptureCardConfig_EthInit("192.168.33.30", "192.168.33.180", "12:34:56:78:90:12", 4096, 4098)
[16:20:59]  [RadarAPI]: ar1.CaptureCardConfig_Mode(1, 2, 1, 2, 3, 30)
[16:20:59]  [RadarAPI]: ar1.CaptureCardConfig_PacketDelay(25)
[16:20:59]  [RadarAPI]: Sending fpga command to DCA1000
[16:21:00]  [RadarAPI]: 
[16:21:00]  FPGA Configuration command : Success
[16:21:00]  [RadarAPI]: Sending record command to DCA1000
[16:21:00]  [RadarAPI]: 
[16:21:00]  Configure Record command : Success
[16:21:00]  [RadarAPI]: ar1.GetCaptureCardFPGAVersion()
[16:21:00]  [RadarAPI]: Sending fpga_version command to DCA1000
[16:21:00]  [RadarAPI]: 
[16:21:00]  
[16:21:00]  FPGA Version : 2.9 [Record]
[16:21:00]  
[16:21:06]  [RadarAPI]: ar1.CaptureCardConfig_StartRecord("C:\\ti\\mmwave_studio_03_01_01_00\\mmWaveStudio\\PostProc\\adc_data.bin", 1)
[16:21:06]  [RadarAPI]: Sending start_record command to DCA1000
[16:21:09]  [RadarAPI]: ar1.StartFrame()
[16:21:09]  [RadarAPI]: Status: Passed
[16:21:09]  Frame start async event received!
[16:21:10]  Frame End async event received!
[16:21:10]  [RadarAPI]: Frame Ended
[16:21:12]  [RadarAPI]: 
[16:21:12]  Start Record command : Success
[16:21:12]  
[16:21:12]  Record is completed
[16:21:12]  
[16:21:12]  Record stop is done successfully
[16:21:12]  [RadarAPI]: 
[16:21:14]  [RadarAPI]: ar1.StartMatlabPostProc("C:\\ti\\mmwave_studio_03_01_01_00\\mmWaveStudio\\PostProc\\adc_data.bin")
[16:21:14]  [RadarAPI]: No of files Captured: 1, Total no of frames for each device : 8
[16:27:22]  [RadarAPI]: ar1.Calling_ATE_DisconnectTarget()
[16:27:22]  [RadarAPI]: ar1.SaveSettings('C:\Users\254300\AppData\Roaming\RSTD\ar1gui.ini')
[16:27:22]  RSTD.ExitRstd()
[16:27:22]  RSTD.SaveSettings(): Settings saved to "C:\Users\254300\AppData\Roaming\RSTD\config.xml"

Attach the log files in the PostProc folder.

Fullscreen 6888.CLI_LogFile.txt Download

Thu Jul 20 15:24:30 2023
Start Record Command (req)

Thu Jul 20 15:24:31 2023
Start Record command : Success

Thu Jul 20 15:24:31 2023
Return status : 0

Thu Jul 20 15:25:51 2023
Record Process : 
Timeout Error! System disconnected

Thu Jul 20 15:25:51 2023
Record stop is done successfully

Thu Jul 20 15:30:54 2023
Start Record Command (req)

Thu Jul 20 15:30:55 2023
Start Record command : Success

Thu Jul 20 15:30:55 2023
Return status : 0

Thu Jul 20 15:32:15 2023
Record Process : 
Timeout Error! System disconnected

Thu Jul 20 15:32:25 2023
Record stop failed

Thu Jul 20 15:34:36 2023
Start Record Command (req)

Thu Jul 20 15:34:36 2023
Start Record command : Success

Thu Jul 20 15:34:36 2023
Return status : 0

Thu Jul 20 15:35:56 2023
Record Process : 
Timeout Error! System disconnected

Thu Jul 20 15:36:06 2023
Record stop failed

Thu Jul 20 16:08:57 2023
Read DLL Verison Command (req)

Thu Jul 20 16:08:57 2023
DLL Version : 1.0

Thu Jul 20 16:09:17 2023
FPGA Configuration Command (req)

Thu Jul 20 16:09:18 2023
FPGA Configuration command : Success

Thu Jul 20 16:09:18 2023
Return status : 0

Thu Jul 20 16:09:18 2023
Configure Record Command (req)

Thu Jul 20 16:09:18 2023
Configure Record command : Success

Thu Jul 20 16:09:18 2023
Return status : 0

Thu Jul 20 16:09:18 2023
Read FPGA version Command (req)

Thu Jul 20 16:09:18 2023

FPGA Version : 2.9 [Record]


Thu Jul 20 16:09:48 2023
Start Record Command (req)

Thu Jul 20 16:09:49 2023
Start Record command : Success

Thu Jul 20 16:09:49 2023
Return status : 0

Thu Jul 20 16:11:09 2023
Record Process : 
Timeout Error! System disconnected

Thu Jul 20 16:11:09 2023
Record stop is done successfully

Thu Jul 20 16:18:30 2023
Read DLL Verison Command (req)

Thu Jul 20 16:18:30 2023
DLL Version : 1.0

Thu Jul 20 16:18:35 2023
FPGA Configuration Command (req)

Thu Jul 20 16:18:35 2023
FPGA Configuration command : Success

Thu Jul 20 16:18:35 2023
Return status : 0

Thu Jul 20 16:18:35 2023
Configure Record Command (req)

Thu Jul 20 16:18:35 2023
Configure Record command : Success

Thu Jul 20 16:18:35 2023
Return status : 0

Thu Jul 20 16:18:35 2023
Read FPGA version Command (req)

Thu Jul 20 16:18:35 2023

FPGA Version : 2.9 [Record]


Thu Jul 20 16:18:40 2023
Reset FPGA Command (req)

Thu Jul 20 16:18:40 2023
Reset FPGA command : Success

Thu Jul 20 16:18:40 2023
Return status : 0

Thu Jul 20 16:18:40 2023
FPGA Configuration Command (req)

Thu Jul 20 16:18:40 2023
FPGA Configuration command : Success

Thu Jul 20 16:18:40 2023
Return status : 0

Thu Jul 20 16:18:40 2023
Configure Record Command (req)

Thu Jul 20 16:18:40 2023
Configure Record command : Success

Thu Jul 20 16:18:40 2023
Return status : 0

Thu Jul 20 16:18:40 2023
Read FPGA version Command (req)

Thu Jul 20 16:18:40 2023

FPGA Version : 2.9 [Record]


Thu Jul 20 16:18:49 2023
Reset FPGA Command (req)

Thu Jul 20 16:18:49 2023
Reset FPGA command : Success

Thu Jul 20 16:18:49 2023
Return status : 0

Thu Jul 20 16:18:49 2023
FPGA Configuration Command (req)

Thu Jul 20 16:18:49 2023
FPGA Configuration command : Success

Thu Jul 20 16:18:49 2023
Return status : 0

Thu Jul 20 16:18:49 2023
Configure Record Command (req)

Thu Jul 20 16:18:49 2023
Configure Record command : Success

Thu Jul 20 16:18:49 2023
Return status : 0

Thu Jul 20 16:18:50 2023
Read FPGA version Command (req)

Thu Jul 20 16:18:50 2023

FPGA Version : 2.9 [Record]


Thu Jul 20 16:19:13 2023
Start Record Command (req)

Thu Jul 20 16:19:13 2023
Start Record command : Success

Thu Jul 20 16:19:13 2023
Return status : 0

Thu Jul 20 16:20:33 2023
Record Process : 
Timeout Error! System disconnected

Thu Jul 20 16:20:34 2023
Record stop is done successfully

Thu Jul 20 16:24:57 2023
Start Record Command (req)

Thu Jul 20 16:24:57 2023
Start Record command : Success

Thu Jul 20 16:24:57 2023
Return status : 0

Thu Jul 20 16:26:17 2023
Record Process : 
Timeout Error! System disconnected

Thu Jul 20 16:26:27 2023
Record stop failed

Thu Jul 20 16:34:09 2023
Start Record Command (req)

Thu Jul 20 16:34:09 2023
Start Record command : Success

Thu Jul 20 16:34:09 2023
Return status : 0

Thu Jul 20 16:34:38 2023
No LVDS data

Thu Jul 20 16:34:38 2023
No Header

Thu Jul 20 16:34:38 2023
Record stop is done successfully

Thu Jul 20 16:35:29 2023
Read DLL Verison Command (req)

Thu Jul 20 16:35:29 2023
DLL Version : 1.0

Thu Jul 20 16:35:31 2023
FPGA Configuration Command (req)

Thu Jul 20 16:35:31 2023
FPGA Configuration command : Success

Thu Jul 20 16:35:31 2023
Return status : 0

Thu Jul 20 16:35:31 2023
Configure Record Command (req)

Thu Jul 20 16:35:31 2023
Configure Record command : Success

Thu Jul 20 16:35:31 2023
Return status : 0

Thu Jul 20 16:35:31 2023
Read FPGA version Command (req)

Thu Jul 20 16:35:31 2023

FPGA Version : 2.9 [Record]


Thu Jul 20 16:35:43 2023
Reset FPGA Command (req)

Thu Jul 20 16:35:43 2023
Reset FPGA command : Success

Thu Jul 20 16:35:43 2023
Return status : 0

Thu Jul 20 16:35:43 2023
FPGA Configuration Command (req)

Thu Jul 20 16:35:43 2023
FPGA Configuration command : Success

Thu Jul 20 16:35:43 2023
Return status : 0

Thu Jul 20 16:35:43 2023
Configure Record Command (req)

Thu Jul 20 16:35:43 2023
Configure Record command : Success

Thu Jul 20 16:35:43 2023
Return status : 0

Thu Jul 20 16:35:43 2023
Read FPGA version Command (req)

Thu Jul 20 16:35:43 2023

FPGA Version : 2.9 [Record]


Thu Jul 20 16:35:53 2023
Start Record Command (req)

Thu Jul 20 16:35:53 2023
Start Record command : Success

Thu Jul 20 16:35:53 2023
Return status : 0

Thu Jul 20 16:37:13 2023
Record Process : 
Timeout Error! System disconnected

Thu Jul 20 16:37:23 2023
Record stop failed

Thu Jul 20 16:51:15 2023
Start Record Command (req)

Thu Jul 20 16:51:15 2023
Start Record command : Success

Thu Jul 20 16:51:15 2023
Return status : 0

Thu Jul 20 16:52:35 2023
Record Process : 
Timeout Error! System disconnected

Thu Jul 20 16:52:35 2023
Record stop is done successfully

Thu Jul 20 16:52:54 2023
Start Record Command (req)

Thu Jul 20 16:52:54 2023
Start Record command : Success

Thu Jul 20 16:52:54 2023
Return status : 0

Thu Jul 20 16:54:14 2023
Record Process : 
Timeout Error! System disconnected

Thu Jul 20 16:54:14 2023
Record stop is done successfully

Thu Jul 20 16:54:40 2023
Read DLL Verison Command (req)

Thu Jul 20 16:54:40 2023
DLL Version : 1.0

Thu Jul 20 16:54:44 2023
FPGA Configuration Command (req)

Thu Jul 20 16:54:44 2023
FPGA Configuration command : Success

Thu Jul 20 16:54:44 2023
Return status : 0

Thu Jul 20 16:54:44 2023
Configure Record Command (req)

Thu Jul 20 16:54:44 2023
Configure Record command : Success

Thu Jul 20 16:54:44 2023
Return status : 0

Thu Jul 20 16:54:44 2023
Read FPGA version Command (req)

Thu Jul 20 16:54:44 2023

FPGA Version : 2.9 [Record]


Thu Jul 20 16:54:53 2023
Start Record Command (req)

Thu Jul 20 16:54:53 2023
Start Record command : Success

Thu Jul 20 16:54:53 2023
Return status : 0

Thu Jul 20 16:55:00 2023
Record is completed

Thu Jul 20 16:55:00 2023
Record stop is done successfully

Thu Jul 20 16:55:33 2023
Start Record Command (req)

Thu Jul 20 16:55:34 2023
Start Record command : Success

Thu Jul 20 16:55:34 2023
Return status : 0

Thu Jul 20 16:55:40 2023
Record is completed

Thu Jul 20 16:55:40 2023
Record stop is done successfully

Tue Aug 01 15:30:45 2023
Start Record Command (req)

Tue Aug 01 15:30:45 2023
Start Record command : Success

Tue Aug 01 15:30:45 2023
Return status : 0

Tue Aug 01 15:32:05 2023
Record Process : 
Timeout Error! System disconnected

Tue Aug 01 15:32:05 2023
Record stop is done successfully

Tue Aug 01 15:41:39 2023
Read DLL Verison Command (req)

Tue Aug 01 15:41:39 2023
DLL Version : 1.0

Tue Aug 01 15:41:45 2023
FPGA Configuration Command (req)

Tue Aug 01 15:41:45 2023
FPGA Configuration command : Success

Tue Aug 01 15:41:45 2023
Return status : 0

Tue Aug 01 15:41:45 2023
Configure Record Command (req)

Tue Aug 01 15:41:45 2023
Configure Record command : Success

Tue Aug 01 15:41:45 2023
Return status : 0

Tue Aug 01 15:41:45 2023
Read FPGA version Command (req)

Tue Aug 01 15:41:45 2023

FPGA Version : 2.9 [Record]


Tue Aug 01 15:45:28 2023
Start Record Command (req)

Tue Aug 01 15:45:29 2023
Start Record command : Success

Tue Aug 01 15:45:29 2023
Return status : 0

Tue Aug 01 15:45:42 2023
Record is completed

Tue Aug 01 15:45:42 2023
Record stop is done successfully

Tue Aug 01 16:13:13 2023
Start Record Command (req)

Tue Aug 01 16:13:13 2023
Start Record command : Success

Tue Aug 01 16:13:13 2023
Return status : 0

Tue Aug 01 16:13:19 2023
Record is completed

Tue Aug 01 16:13:19 2023
Record stop is done successfully

Tue Aug 01 16:19:29 2023
Start Record Command (req)

Tue Aug 01 16:19:30 2023
Start Record command : Success

Tue Aug 01 16:19:30 2023
Return status : 0

Tue Aug 01 16:19:34 2023
Record is completed

Tue Aug 01 16:19:34 2023
Record stop is done successfully

Tue Aug 01 16:20:27 2023
Start Record Command (req)

Tue Aug 01 16:20:28 2023
Start Record command : Success

Tue Aug 01 16:20:28 2023
Return status : 0

Tue Aug 01 16:20:33 2023
Record is completed

Tue Aug 01 16:20:33 2023
Record stop is done successfully

Tue Aug 01 16:27:29 2023
Start Record Command (req)

Tue Aug 01 16:27:30 2023
Start Record command : Success

Tue Aug 01 16:27:30 2023
Return status : 0

Tue Aug 01 16:27:41 2023
Record is completed

Tue Aug 01 16:27:41 2023
Record stop is done successfully

Tue Aug 01 16:30:02 2023
Start Record Command (req)

Tue Aug 01 16:30:02 2023
Start Record command : Success

Tue Aug 01 16:30:02 2023
Return status : 0

Tue Aug 01 16:30:09 2023
Record is completed

Tue Aug 01 16:30:09 2023
Record stop is done successfully

Tue Aug 01 16:36:25 2023
Start Record Command (req)

Tue Aug 01 16:36:25 2023
Start Record command : Success

Tue Aug 01 16:36:25 2023
Return status : 0

Tue Aug 01 16:36:31 2023
Record is completed

Tue Aug 01 16:36:31 2023
Record stop is done successfully

Tue Aug 01 16:41:37 2023
Start Record Command (req)

Tue Aug 01 16:41:37 2023
Start Record command : Success

Tue Aug 01 16:41:37 2023
Return status : 0

Tue Aug 01 16:41:42 2023
Record is completed

Tue Aug 01 16:41:42 2023
Record stop is done successfully

Tue Aug 01 16:43:14 2023
Start Record Command (req)

Tue Aug 01 16:43:14 2023
Start Record command : Success

Tue Aug 01 16:43:14 2023
Return status : 0

Tue Aug 01 16:43:19 2023
Record is completed

Tue Aug 01 16:43:19 2023
Record stop is done successfully

Tue Aug 01 17:08:58 2023
Read DLL Verison Command (req)

Tue Aug 01 17:08:58 2023
DLL Version : 1.0

Tue Aug 01 17:09:01 2023
FPGA Configuration Command (req)

Tue Aug 01 17:09:01 2023
FPGA Configuration command : Success

Tue Aug 01 17:09:01 2023
Return status : 0

Tue Aug 01 17:09:01 2023
Configure Record Command (req)

Tue Aug 01 17:09:01 2023
Configure Record command : Success

Tue Aug 01 17:09:01 2023
Return status : 0

Tue Aug 01 17:09:01 2023
Read FPGA version Command (req)

Tue Aug 01 17:09:01 2023

FPGA Version : 2.9 [Record]


Tue Aug 01 17:09:47 2023
Start Record Command (req)

Tue Aug 01 17:09:47 2023
Start Record command : Success

Tue Aug 01 17:09:47 2023
Return status : 0

Tue Aug 01 17:09:54 2023
Record is completed

Tue Aug 01 17:09:54 2023
Record stop is done successfully

Tue Aug 01 18:24:28 2023
Start Record Command (req)

Tue Aug 01 18:24:28 2023
Start Record command : Success

Tue Aug 01 18:24:28 2023
Return status : 0

Tue Aug 01 18:25:48 2023
Record Process : 
Timeout Error! System disconnected

Tue Aug 01 18:25:48 2023
Record stop is done successfully

Tue Aug 01 18:27:01 2023
FPGA Configuration Command (req)

Tue Aug 01 18:27:01 2023
FPGA Configuration command : Success

Tue Aug 01 18:27:01 2023
Return status : 0

Tue Aug 01 18:27:01 2023
Configure Record Command (req)

Tue Aug 01 18:27:01 2023
Configure Record command : Success

Tue Aug 01 18:27:01 2023
Return status : 0

Tue Aug 01 18:27:01 2023
Read FPGA version Command (req)

Tue Aug 01 18:27:01 2023

FPGA Version : 2.9 [Record]


Tue Aug 01 18:27:35 2023
Start Record Command (req)

Tue Aug 01 18:27:35 2023
Start Record command : Success

Tue Aug 01 18:27:35 2023
Return status : 0

Tue Aug 01 18:27:40 2023
Record is completed

Tue Aug 01 18:27:40 2023
Record stop is done successfully

Tue Aug 01 19:25:57 2023
Start Record Command (req)

Tue Aug 01 19:25:57 2023
Start Record command : Success

Tue Aug 01 19:25:57 2023
Return status : 0

Tue Aug 01 19:26:03 2023
Record is completed

Tue Aug 01 19:26:03 2023
Record stop is done successfully

Tue Aug 01 19:38:33 2023
FPGA Configuration Command (req)

Tue Aug 01 19:38:33 2023
FPGA Configuration command : Success

Tue Aug 01 19:38:33 2023
Return status : 0

Tue Aug 01 19:38:33 2023
Configure Record Command (req)

Tue Aug 01 19:38:33 2023
Configure Record command : Success

Tue Aug 01 19:38:33 2023
Return status : 0

Tue Aug 01 19:38:33 2023
Read FPGA version Command (req)

Tue Aug 01 19:38:33 2023

FPGA Version : 2.9 [Record]


Tue Aug 01 19:38:40 2023
Start Record Command (req)

Tue Aug 01 19:38:41 2023
Start Record command : Success

Tue Aug 01 19:38:41 2023
Return status : 0

Tue Aug 01 19:38:46 2023
Record is completed

Tue Aug 01 19:38:46 2023
Record stop is done successfully

Tue Aug 01 19:58:15 2023
FPGA Configuration Command (req)

Tue Aug 01 19:58:16 2023
FPGA Configuration command : Success

Tue Aug 01 19:58:16 2023
Return status : 0

Tue Aug 01 19:58:16 2023
Configure Record Command (req)

Tue Aug 01 19:58:16 2023
Configure Record command : Success

Tue Aug 01 19:58:16 2023
Return status : 0

Tue Aug 01 19:58:16 2023
Read FPGA version Command (req)

Tue Aug 01 19:58:16 2023

FPGA Version : 2.9 [Record]


Tue Aug 01 19:58:20 2023
Start Record Command (req)

Tue Aug 01 19:58:20 2023
Start Record command : Success

Tue Aug 01 19:58:20 2023
Return status : 0

Tue Aug 01 19:58:50 2023
No LVDS data

Tue Aug 01 19:58:50 2023
Record stop is done successfully

Tue Aug 01 20:00:29 2023
FPGA Configuration Command (req)

Tue Aug 01 20:00:30 2023
FPGA Configuration command : Success

Tue Aug 01 20:00:30 2023
Return status : 0

Tue Aug 01 20:00:30 2023
Configure Record Command (req)

Tue Aug 01 20:00:30 2023
Configure Record command : Success

Tue Aug 01 20:00:30 2023
Return status : 0

Tue Aug 01 20:00:30 2023
Read FPGA version Command (req)

Tue Aug 01 20:00:30 2023

FPGA Version : 2.9 [Record]


Tue Aug 01 20:00:35 2023
Start Record Command (req)

Tue Aug 01 20:00:35 2023
Start Record command : Success

Tue Aug 01 20:00:35 2023
Return status : 0

Tue Aug 01 20:00:40 2023
Record is completed

Tue Aug 01 20:00:40 2023
Record stop is done successfully

Thu Aug 03 16:43:25 2023
Read DLL Verison Command (req)

Thu Aug 03 16:43:25 2023
DLL Version : 1.0

Thu Aug 03 16:43:27 2023
FPGA Configuration Command (req)

Thu Aug 03 16:43:28 2023
FPGA Configuration command : Success

Thu Aug 03 16:43:28 2023
Return status : 0

Thu Aug 03 16:43:28 2023
Configure Record Command (req)

Thu Aug 03 16:43:28 2023
Configure Record command : Success

Thu Aug 03 16:43:28 2023
Return status : 0

Thu Aug 03 16:43:28 2023
Read FPGA version Command (req)

Thu Aug 03 16:43:28 2023

FPGA Version : 2.9 [Record]


Thu Aug 03 16:43:46 2023
Start Record Command (req)

Thu Aug 03 16:43:46 2023
Start Record command : Success

Thu Aug 03 16:43:46 2023
Return status : 0

Thu Aug 03 16:43:51 2023
Record is completed

Thu Aug 03 16:43:51 2023
Record stop is done successfully

Thu Aug 03 16:45:51 2023
Start Record Command (req)

Thu Aug 03 16:45:52 2023
Start Record command : Success

Thu Aug 03 16:45:52 2023
Return status : 0

Thu Aug 03 16:46:05 2023
Record is completed

Thu Aug 03 16:46:05 2023
Record stop is done successfully

Thu Aug 03 16:57:14 2023
Start Record Command (req)

Thu Aug 03 16:57:14 2023
Start Record command : Success

Thu Aug 03 16:57:14 2023
Return status : 0

Thu Aug 03 16:57:18 2023
Record is completed

Thu Aug 03 16:57:18 2023
Record stop is done successfully

Thu Aug 03 17:32:14 2023
FPGA Configuration Command (req)

Thu Aug 03 17:32:14 2023
FPGA Configuration command : Success

Thu Aug 03 17:32:14 2023
Return status : 0

Thu Aug 03 17:32:14 2023
Configure Record Command (req)

Thu Aug 03 17:32:14 2023
Configure Record command : Success

Thu Aug 03 17:32:14 2023
Return status : 0

Thu Aug 03 17:32:14 2023
Read FPGA version Command (req)

Thu Aug 03 17:32:14 2023

FPGA Version : 2.9 [Record]


Thu Aug 03 18:06:06 2023
Read DLL Verison Command (req)

Thu Aug 03 18:06:06 2023
DLL Version : 1.0

Thu Aug 03 18:06:08 2023
FPGA Configuration Command (req)

Thu Aug 03 18:06:08 2023
FPGA Configuration command : Success

Thu Aug 03 18:06:08 2023
Return status : 0

Thu Aug 03 18:06:08 2023
Configure Record Command (req)

Thu Aug 03 18:06:08 2023
Configure Record command : Success

Thu Aug 03 18:06:08 2023
Return status : 0

Thu Aug 03 18:06:09 2023
Read FPGA version Command (req)

Thu Aug 03 18:06:09 2023

FPGA Version : 2.9 [Record]


Thu Aug 03 18:07:03 2023
Start Record Command (req)

Thu Aug 03 18:07:03 2023
Start Record command : Success

Thu Aug 03 18:07:03 2023
Return status : 0

Thu Aug 03 18:07:33 2023
No LVDS data

Thu Aug 03 18:07:33 2023
Record stop is done successfully

Thu Aug 03 18:08:07 2023
Start Record Command (req)

Thu Aug 03 18:08:07 2023
Start Record command : Success

Thu Aug 03 18:08:07 2023
Return status : 0

Thu Aug 03 18:08:12 2023
Record is completed

Thu Aug 03 18:08:12 2023
Record stop is done successfully

Thu Aug 03 18:13:26 2023
Start Record Command (req)

Thu Aug 03 18:13:26 2023
Start Record command : Success

Thu Aug 03 18:13:26 2023
Return status : 0

Thu Aug 03 18:13:34 2023
EEPROM Failure

Thu Aug 03 18:13:55 2023
No LVDS data

Thu Aug 03 18:13:55 2023
No Header

Thu Aug 03 18:13:55 2023
Record stop is done successfully

Thu Aug 03 18:14:43 2023
Start Record Command (req)

Thu Aug 03 18:14:44 2023
Start Record command : Success

Thu Aug 03 18:14:44 2023
Return status : 0

Thu Aug 03 18:16:04 2023
Record Process : 
Timeout Error! System disconnected

Thu Aug 03 18:16:04 2023
Record stop is done successfully

Thu Aug 03 18:16:41 2023
Start Record Command (req)

Thu Aug 03 18:16:41 2023
Start Record command : Success

Thu Aug 03 18:16:41 2023
Return status : 0

Thu Aug 03 18:18:01 2023
Record Process : 
Timeout Error! System disconnected

Thu Aug 03 18:18:02 2023
Record stop is done successfully

Thu Aug 03 18:18:46 2023
Start Record Command (req)

Thu Aug 03 18:18:47 2023
Start Record command : Success

Thu Aug 03 18:18:47 2023
Return status : 0

Thu Aug 03 18:20:07 2023
Record Process : 
Timeout Error! System disconnected

Thu Aug 03 18:20:07 2023
Record stop is done successfully

Thu Aug 03 18:20:38 2023
Start Record Command (req)

Thu Aug 03 18:20:38 2023
Start Record command : Success

Thu Aug 03 18:20:38 2023
Return status : 0

Thu Aug 03 18:21:58 2023
Record Process : 
Timeout Error! System disconnected

Thu Aug 03 18:21:59 2023
Record stop is done successfully

Thu Aug 03 18:22:16 2023
FPGA Configuration Command (req)

Thu Aug 03 18:22:16 2023
FPGA Configuration command : Success

Thu Aug 03 18:22:16 2023
Return status : 0

Thu Aug 03 18:22:16 2023
Configure Record Command (req)

Thu Aug 03 18:22:16 2023
Configure Record command : Success

Thu Aug 03 18:22:16 2023
Return status : 0

Thu Aug 03 18:22:16 2023
Read FPGA version Command (req)

Thu Aug 03 18:22:16 2023

FPGA Version : 2.9 [Record]


Thu Aug 03 18:22:22 2023
Start Record Command (req)

Thu Aug 03 18:22:22 2023
Start Record command : Success

Thu Aug 03 18:22:22 2023
Return status : 0

Thu Aug 03 18:22:28 2023
Record is completed

Thu Aug 03 18:22:28 2023
Record stop is done successfully

Thu Aug 03 18:23:04 2023
FPGA Configuration Command (req)

Thu Aug 03 18:23:05 2023
FPGA Configuration command : Success

Thu Aug 03 18:23:05 2023
Return status : 0

Thu Aug 03 18:23:05 2023
Configure Record Command (req)

Thu Aug 03 18:23:05 2023
Configure Record command : Success

Thu Aug 03 18:23:05 2023
Return status : 0

Thu Aug 03 18:23:05 2023
Read FPGA version Command (req)

Thu Aug 03 18:23:05 2023

FPGA Version : 2.9 [Record]


Thu Aug 03 18:23:11 2023
Start Record Command (req)

Thu Aug 03 18:23:11 2023
Start Record command : Success

Thu Aug 03 18:23:11 2023
Return status : 0

Thu Aug 03 18:23:26 2023
Record is completed

Thu Aug 03 18:23:26 2023
Record stop is done successfully

Thu Aug 03 18:24:41 2023
Start Record Command (req)

Thu Aug 03 18:24:41 2023
Start Record command : Success

Thu Aug 03 18:24:41 2023
Return status : 0

Thu Aug 03 18:25:02 2023
Record is completed

Thu Aug 03 18:25:02 2023
Record stop is done successfully

Thu Aug 03 19:40:00 2023
FPGA Configuration Command (req)

Thu Aug 03 19:40:00 2023
FPGA Configuration command : Success

Thu Aug 03 19:40:00 2023
Return status : 0

Thu Aug 03 19:40:00 2023
Configure Record Command (req)

Thu Aug 03 19:40:00 2023
Configure Record command : Success

Thu Aug 03 19:40:00 2023
Return status : 0

Thu Aug 03 19:40:00 2023
Read FPGA version Command (req)

Thu Aug 03 19:40:00 2023

FPGA Version : 2.9 [Record]


Thu Aug 03 19:40:06 2023
Start Record Command (req)

Thu Aug 03 19:40:06 2023
Start Record command : Success

Thu Aug 03 19:40:06 2023
Return status : 0

Thu Aug 03 19:40:33 2023
Record is completed

Thu Aug 03 19:40:33 2023
Record stop is done successfully

Fri Aug 04 17:55:15 2023
Read DLL Verison Command (req)

Fri Aug 04 17:55:15 2023
DLL Version : 1.0

Fri Aug 04 17:55:17 2023
FPGA Configuration Command (req)

Fri Aug 04 17:55:23 2023
Ethernet connection (req)

Fri Aug 04 17:55:23 2023
Ethernet connection failed. [error -4051]

Fri Aug 04 17:55:27 2023
FPGA Configuration : 
Timeout Error! System disconnected

Fri Aug 04 17:55:27 2023
Return status : -5

Fri Aug 04 17:55:27 2023
Configure Record Command (req)

Fri Aug 04 17:55:37 2023
Configure Record : 
Timeout Error! System disconnected

Fri Aug 04 17:55:37 2023
Return status : -5

Fri Aug 04 17:55:37 2023
Read FPGA version Command (req)

Fri Aug 04 17:55:47 2023

Unable to read FPGA Version. [error -5]


Fri Aug 04 17:58:40 2023
Start Record Command (req)

Fri Aug 04 17:58:50 2023
Start Record : 
Timeout Error! System disconnected

Fri Aug 04 17:58:50 2023
Return status : -5

Fri Aug 04 17:59:37 2023
Start Record Command (req)

Fri Aug 04 17:59:37 2023
Start Record command : Success

Fri Aug 04 17:59:37 2023
Return status : 0

Fri Aug 04 18:00:06 2023
No LVDS data

Fri Aug 04 18:00:06 2023
No Header

Fri Aug 04 18:00:06 2023
Record stop is done successfully

Fri Aug 04 18:00:14 2023
Start Record Command (req)

Fri Aug 04 18:00:14 2023
Start Record command : Success

Fri Aug 04 18:00:14 2023
Return status : 0

Fri Aug 04 18:00:43 2023
No LVDS data

Fri Aug 04 18:00:43 2023
No Header

Fri Aug 04 18:00:43 2023
Record stop is done successfully

Fri Aug 04 18:00:48 2023
FPGA Configuration Command (req)

Fri Aug 04 18:00:48 2023
FPGA Configuration command : Success

Fri Aug 04 18:00:48 2023
Return status : 0

Fri Aug 04 18:00:48 2023
Configure Record Command (req)

Fri Aug 04 18:00:48 2023
Configure Record command : Success

Fri Aug 04 18:00:48 2023
Return status : 0

Fri Aug 04 18:00:48 2023
Read FPGA version Command (req)

Fri Aug 04 18:00:48 2023

FPGA Version : 2.9 [Record]


Fri Aug 04 18:00:55 2023
Start Record Command (req)

Fri Aug 04 18:00:55 2023
Start Record command : Success

Fri Aug 04 18:00:55 2023
Return status : 0

Fri Aug 04 18:01:01 2023
Record is completed

Fri Aug 04 18:01:01 2023
Record stop is done successfully

Fri Aug 04 18:03:48 2023
Read DLL Verison Command (req)

Fri Aug 04 18:03:48 2023
DLL Version : 1.0

Fri Aug 04 18:03:50 2023
FPGA Configuration Command (req)

Fri Aug 04 18:03:50 2023
FPGA Configuration command : Success

Fri Aug 04 18:03:50 2023
Return status : 0

Fri Aug 04 18:03:50 2023
Configure Record Command (req)

Fri Aug 04 18:03:50 2023
Configure Record command : Success

Fri Aug 04 18:03:50 2023
Return status : 0

Fri Aug 04 18:03:51 2023
Read FPGA version Command (req)

Fri Aug 04 18:03:51 2023

FPGA Version : 2.9 [Record]


Fri Aug 04 18:03:56 2023
Start Record Command (req)

Fri Aug 04 18:03:56 2023
Start Record command : Success

Fri Aug 04 18:03:56 2023
Return status : 0

Fri Aug 04 18:04:00 2023
Record is completed

Fri Aug 04 18:04:00 2023
Record stop is done successfully

Thu Aug 10 18:26:04 2023
Read DLL Verison Command (req)

Thu Aug 10 18:26:04 2023
DLL Version : 1.0

Thu Aug 10 18:26:46 2023
FPGA Configuration Command (req)

Thu Aug 10 18:26:56 2023
FPGA Configuration : 
Timeout Error! System disconnected

Thu Aug 10 18:26:56 2023
Return status : -5

Thu Aug 10 18:26:56 2023
Configure Record Command (req)

Thu Aug 10 18:27:06 2023
Configure Record : 
Timeout Error! System disconnected

Thu Aug 10 18:27:06 2023
Return status : -5

Thu Aug 10 18:27:06 2023
Read FPGA version Command (req)

Thu Aug 10 18:27:16 2023

Unable to read FPGA Version. [error -5]


Thu Aug 10 18:44:14 2023
FPGA Configuration Command (req)

Thu Aug 10 18:44:24 2023
FPGA Configuration : 
Timeout Error! System disconnected

Thu Aug 10 18:44:24 2023
Return status : -5

Thu Aug 10 18:44:24 2023
Configure Record Command (req)

Thu Aug 10 18:44:34 2023
Configure Record : 
Timeout Error! System disconnected

Thu Aug 10 18:44:34 2023
Return status : -5

Thu Aug 10 18:44:34 2023
Read FPGA version Command (req)

Thu Aug 10 18:44:44 2023

Unable to read FPGA Version. [error -5]


Wed Aug 16 13:05:30 2023
Read DLL Verison Command (req)

Wed Aug 16 13:05:30 2023
DLL Version : 1.0

Wed Aug 16 15:36:52 2023
Read DLL Verison Command (req)

Wed Aug 16 15:36:52 2023
DLL Version : 1.0

Wed Aug 16 15:36:55 2023
FPGA Configuration Command (req)

Wed Aug 16 15:36:55 2023
FPGA Configuration command : Success

Wed Aug 16 15:36:55 2023
Return status : 0

Wed Aug 16 15:36:55 2023
Configure Record Command (req)

Wed Aug 16 15:36:55 2023
Configure Record command : Success

Wed Aug 16 15:36:55 2023
Return status : 0

Wed Aug 16 15:36:55 2023
Read FPGA version Command (req)

Wed Aug 16 15:36:55 2023

FPGA Version : 2.9 [Record]


Wed Aug 16 15:37:19 2023
Start Record Command (req)

Wed Aug 16 15:37:19 2023
Start Record command : Success

Wed Aug 16 15:37:19 2023
Return status : 0

Wed Aug 16 15:37:25 2023
Record is completed

Wed Aug 16 15:37:25 2023
Record stop is done successfully

Wed Aug 16 16:20:59 2023
FPGA Configuration Command (req)

Wed Aug 16 16:21:00 2023
FPGA Configuration command : Success

Wed Aug 16 16:21:00 2023
Return status : 0

Wed Aug 16 16:21:00 2023
Configure Record Command (req)

Wed Aug 16 16:21:00 2023
Configure Record command : Success

Wed Aug 16 16:21:00 2023
Return status : 0

Wed Aug 16 16:21:00 2023
Read FPGA version Command (req)

Wed Aug 16 16:21:00 2023

FPGA Version : 2.9 [Record]


Wed Aug 16 16:21:06 2023
Start Record Command (req)

Wed Aug 16 16:21:06 2023
Start Record command : Success

Wed Aug 16 16:21:06 2023
Return status : 0

Wed Aug 16 16:21:11 2023
Record is completed

Wed Aug 16 16:21:11 2023
Record stop is done successfully

Fullscreen 7167.LogFile.txt Download

16-Aug-2023 15:27:52: IsFPGA:,0,0,
16-Aug-2023 15:27:53: C:\ti\mmwave_studio_03_01_01_00\mmWaveStudio\RunTime,0,
16-Aug-2023 15:27:56: API:select_capture_device,DCA1000,0,
16-Aug-2023 15:31:11: API:select_chip_version,AR1642,0,
16-Aug-2023 15:32:13: API:ChannelConfig,15,15,0,
16-Aug-2023 15:32:13: API:AdcOutConfig,2,0,0,
16-Aug-2023 15:32:13: API:DataFmtConfig,15,2,0,0,1,0,
16-Aug-2023 15:32:15: API:LowPowerConfig,0,0,0,
16-Aug-2023 15:32:28: API:DataPathConfig,1,1,0,2,0,
16-Aug-2023 15:32:31: API:LvdsClkConfig,1,1,0,
16-Aug-2023 15:32:31: TSW1400 Sampling rate : 600000000 7500000,0,
16-Aug-2023 15:32:31: API:SetHsiClock,9,0,
16-Aug-2023 15:32:33: API:LaneConfig,3,0,
16-Aug-2023 15:32:33: API:LvdsLaneConfig,0,1,0,
16-Aug-2023 15:34:02: API:ProfileConfig,0,1435384036,10000,600,6000,0,0,621,0,256,10000,0,0,30,0,
16-Aug-2023 15:34:23: API:ChirpConfig,0,0,0,0,0,0,0,1,0,
16-Aug-2023 15:34:30: API:ChirpConfig,1,1,0,0,0,0,0,2,0,
16-Aug-2023 15:34:36: API:ChirpConfig,2,2,0,0,0,0,0,4,0,
16-Aug-2023 15:34:41: API:ChirpConfig,3,3,0,0,0,0,0,8,0,
16-Aug-2023 15:35:53: API:EnableTestSource,0,1,0,
16-Aug-2023 15:35:53: API:FrameConfig,0,3,8,60,8000000,0,256,0,
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16-Aug-2023 15:36:52: API:select_capture_device,DCA1000,0,
16-Aug-2023 15:36:52: API:update_device_map,1,0,
16-Aug-2023 15:37:22: API:SensorStart,0,
16-Aug-2023 15:37:36: API:update_num_adc_files_and_frames,1,8,1,0,
16-Aug-2023 15:39:12: Play as movie ,0,0,
16-Aug-2023 16:20:31: API:ChirpConfig,3,3,0,0,0,0,0,0,0,
16-Aug-2023 16:20:49: API:update_device_map,1,0,
16-Aug-2023 16:21:09: API:SensorStart,0,
16-Aug-2023 16:21:14: API:update_num_adc_files_and_frames,1,8,1,0,

Attach the CSV file used in the Chirp Manager.

7245.ChirpConfigData.csv

Our customer wants to configure for TDM-MIMO with 4TX and 4RX.

Best regards,

Daisuke

0 Saswat Kumar over 2 years ago in reply to Daisuke Maeda

TI__Mastermind 35715 points

Hello Daisuke,

Let me check this with the team and get back to you.

Regards,
Saswat Kumar

0 Daisuke Maeda over 2 years ago in reply to Saswat Kumar

Guru 20205 points

Hi Saswat-san,

Thank you for your support. Our customer is waiting for your response.

Daisuke Maeda said:
Our customer wants to configure for TDM-MIMO with 4TX and 4RX.

Does the log in the output window show that it is configured for TDM-MIMO with 4TX and 4RX?

Daisuke Maeda said:
Attach the CSV file used in the Chirp Manager.

Are there any errors in the CSV file?

Please give me an answer as soon as possible. Your prompt reply would be appreciated.

Best regards,

Daisuke

0 Saswat Kumar over 2 years ago in reply to Daisuke Maeda

TI__Mastermind 35715 points

Hello Daisuke,

The team is working on recreating it, please expect some response tomorrow.

Regards,
Saswat Kumar

+1 Saswat Kumar over 2 years ago in reply to Saswat Kumar

TI__Mastermind 35715 points

Hello Daisuke,

The configuration is right, we are unable to see any such error when I am using the same.

Regards,
Saswat Kumar

0 Daisuke Maeda over 2 years ago in reply to Saswat Kumar

Guru 20205 points

Hi Saswat-san,

Thank you for your reply.

I understand that the log in the output window shows to be configured for TDM-MIMO with 4TX and 4RX.

We see the error shown in my first post when activating after loading the CSV file in Chirp Manager.

Cannot reproduce the error?

Best regards,

Daisuke

0 Saswat Kumar over 2 years ago in reply to Daisuke Maeda

TI__Mastermind 35715 points

Hello Daisuke,

Can you share with me the CSV files and the exact steps from opening the mmwave studio to when you load the chirp manager and face the issue so I can reproduce it?

Regards,
Saswat Kumar

0 Daisuke Maeda over 2 years ago in reply to Saswat Kumar

Guru 20205 points

Hi Saswat-san,

Thank you for your reply.

In my environment, after successfully executing the initialization script, immediately start the Chirp Manager, load the CSV file attached in my post above, and activate it, and the error is reproduced.

Best regards,

Daisuke

0 Saswat Kumar over 2 years ago in reply to Daisuke Maeda

TI__Mastermind 35715 points

Hello Daisuke,

Here are the steps I followed:
1) First set the basic config and then click on RF power up:

2) Then went to the chirp config manager and you can see it had a default value set:

3) Then I loaded the file provided by you after renaming it and it loaded successfully:

I only observed an issue if the CSV was open in some other tab and then I tried to load it in the chirp manager simultaneously or else I do not see any issue as such while loading.

Regards,
Saswat Kumar

0 Daisuke Maeda over 2 years ago in reply to Saswat Kumar

Guru 20205 points

Hi Saswat-san,

Thank you for your reply.

Please let me confirm one point.

Did you press "Activate" after "Load" the CSV file? Do you get no error after that?

I do not have the board at hand so I cannot try it right away.

Best regards,

Daisuke

+1 Saswat Kumar over 2 years ago in reply to Daisuke Maeda

TI__Mastermind 35715 points

Hello Daisuke-san,

I checked with the activate it is not working.
I checked with the team it is a known issue, please advise customer not to use this.
There is no current timeline of this when it will be fixed.

Regards,
Saswat Kumar

0 Daisuke Maeda over 2 years ago in reply to Saswat Kumar

Guru 20205 points

Hi Saswat-san,

Thank you for your reply.

We will wait for the issue to be fixed.

For other evaluation modules, a lua script for demo is provided, but for the AWR2944EVM, it is not provided.

Will a lua script for demo for AWR2944EVM be provided in mmWave Studio which is scheduled to be released in the future?

Best regards,

Daisuke

0 Saswat Kumar over 2 years ago in reply to Daisuke Maeda

TI__Mastermind 35715 points

Hello Daisuke,

There is no plan for that, it is very easy to generate the same, from the output window you can collect the samples and then save it in a lua script and then load the lua and execute.

Regards,
Saswat Kumar

0 Daisuke Maeda over 2 years ago in reply to Saswat Kumar

Guru 20205 points

Hi Saswat-san,

Thank you for your reply.

Our customers used a demo lua script for other evaluation modules as a reference for configuration, so we would like to strongly request that it be provided for AWR2944EVM in a future release.

Best regards,

Daisuke

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AWR2944EVM: Issue with the mmWave Studio