FDC2112: input signal

Hi John

if I use the diff mode instead of the single end mode, the input signal still needs to resemble a half-wave rectified sinusoids? can it  be a sinusoid between the diff end.and i want ask you about how  does the internal core realize frequency count?  

Thx.

Hi John，

I got it, but i want to ask a new question about the input is an asymtemetric  signal ，the negative half wave is  not as the as the positive half. does it matter in diff input mode? will it affect the measure result?

Eric,

The asymmetrical shape may indeed affect the results, particularly since the upper half of the waveform appears to have a different duration than the bottom half of the waveform.

But before we take that much further, can you probe the two pins single-separately - showing the ground references -  and post the waveforms to this thread?

Regards,
John

Hi John,

I,m  sorry for getting back to you late but after i discussed with the engineer, I have know the actual problems，

first of all， can you help me to check  how the core calculate the input signal frequency just refer my hand script (picture 1). can you show me more about this？

the second is the input signal just like the upload picture before. that is the actual signal they tested, for the input signal ,we can see the up half wave has some spurs, but if they  increase  the input signal's amplitude to 2 voltage even more, the output keep stable, but if they change the input signal's amplitude to 1.2v-1.8v,the output will jump random. so we guess that when the input signal amplitude large enough ,it will beyond the acquisition zone(1.2V-1.8V),and  the original signals will be sampled in the  fixed point as the normal signal just refer the picture 2

Thx.

Eric,

Thank you for the additional information.
The FDC2112 is counting axis crossings of a sensor signal that should look like a sinusoid when measured differentially across the input pins.
The axis crossings of the differential sensor signal are counted during an interval specified by the number of axis crossings of the reference clock as specified by RCOUNTx. As your diagrams show, the customer's sensor signal looks to have a number of sinusoids in it, and this is probably messing up the axis crossing counts.

A few questions:
1. In the original photo of their waveform, does the center horizontal axis correspond to ground?
2. Can they provide a schematic and BOM of their design?
3. What waveforms do they see when they probe the two input pins separately?
    Can they provide snaps of those signals?
4. Are they using a 40MHz external reference clock? If they are, can they verify it is clean and stable?

Regards,
John

Hi John，

In the actual use process, the baseline of the signal is below 0V, -0.2V or so, they have tested, it is indeed due to waveform distortion caused by the measurement results are wrong. The measurement waveform distortion is caused by the addition of EMI filtering to the signal input, remove the EMI filter circuit, the input signal is a perfect sine wave, and the test result is correct. Secondly, I want to understand the specific method of signal crossing the axis, is it like I described? If so, how to quantify the exact location of the intersection. Second, customers can ensure stable output by increasing the amplitude of the input signal. The customer wants to know where the specific internal crossover occurs, and whether it can ensure stability if the signal amplitude exceeds (1.2V-1.8V) and works for a long time.

Hi John，

i want konw how the axis corssed by the input signal is a baseline （the axisjust like a x axisand it's about  0v or another direct voltage？）can you show me how the signal cross the axis.this may influent the follow steps we need to act.and i want to have a webex meeting with you ,can we shchdule a claendar.

Thx.

Hi Jhon，

Thank you for your response. I got it. I have another question about this chip, if the signal amplitude exceeds 1.8V(1.8V -VDD), if the chip will be destroyed for a long time in this case ? 

Hi John,  I've been reading some of these other threads and I have a question here. 

You mention that the device is measuring the axis crossings at ground 0V. You also say that increasing the amplitude of the waveform may cause it to clip and reduce the device's accuracy.  If the waveform is increased and it starts to clip, I would assume it would look square, with only the 2 certain crossings of the axis per period.

Could you explain a bit more as to why the larger amplitude could reduce the device's accuracy?

Thanks,

Hadyn

Hi John，

The customer is currently asking a question about the FDC2112 and they want to know what exactly this 0V reference line, which is the baseline through which the oscillating waveform travels in a differential application. Is the GND signal? But in a differential application, our power supply is only positive, no negative voltage, so how do our internal circuits capture a negative signal, At this point the crossing reference line is 0V or 1/2VDD ?

Hi Jhon,

I would like to ask the customer whether we can know exactly what the level is and whether there is a formula to calculate it. Also for single-ended and differential applications, the differential signal has a positive and negative half cycle and the chip is powered from a single power supply. how negative signals are captured inside the chip. If the level is passed, is the level automatically adjusted internally? 

Thanks

Hi Jhon,

First of all, thank you very much for your reply. For me, I already know a lot about the use of this chip. but you also need to know some of the details that you're talking about. For the internal count you're talking about, I already know that it's going to be in a fixed time window to calculate the number of times the LC oscillation signal crosses the reference reference baseline, and so I'm going to get the frequency of the oscillation signal, but I need to have an absolute definition for the specific value of the reference baseline. For example, in the case of differential inputs, is the reference line referenced to (Vdd/2) or GND? For single-ended input, is the signal cross GND or a fixed DC level as a reference line? At this time, the customer is very concerned about this issue, so I look forward to your response. We would rather get an exact answer.

Thanks,

Eric.

Hi Jhon,

For the differential mode, the signal must have the positive half wave and the negative half wave .for the core， how it can sample a negative signal if there is any internal charge pump used to provide a negative power supply for the chip and  I think the GND reference line just like a comparator ，once the signal cross the GND，there will be a signal change just like rising edge or falling edge .if the internal works like this ，i need to know the comparator is a zero-crossing comparator or a hysteresis comparator？if it is a hysteresis comparator ,what is its tolerance range, the reference line's  vlotage level may not be a absolute value. 

Thanks.

Hi Jhon，

but for the negative half wave ，how it can sample such a signal ，the signal just have a positive power supply，unless there is a charge pump used to generate a negative power

Hi

The Vin(Voltage on any pin) written by FDC2112 does not exceed VDD0.3 (3.3V power supply, so this voltage is 3.6V)

Based on the internal principle of this chip, for the two pins of differential input, does this voltage mean that the peak of the differential signal does not exceed 3.6V, or does it mean that the single-end ground-to-ground voltage of the differential pin does not exceed 3.6V? Please confirm this problem. Thank you.

Hi Jhon， is there any charge pump in chip ？if there is no ，how the chip can sample the diff signal ,the diff signal has both the positive and negative half wave.