AWR2944: Inquiry regarding memory consistency between MSS and DSS by HW

Due to local holidays we will be able to get back to you second half of the week.

thank you

Cesar

Hi,

For this case we have the MPU and the L3 memory design. The L3 memory has 4 banks. Each bank can be provided different configurations with the MPU. For example, say bank1 only the MSS will have write access and DSS will have read access. Similarly, bank2 can have the reverse condition. 

There is no HW semaphore or gate available for this use case as per your query.

Also, would like to understand the use case form your side more clearly or in some detail as to why you will not be using the mailbox but L3 memory. Which data do you want to transfer?  This will help us in understanding your use case better and suggesting a better solution if available.

Thanks,

Pradipta.

Hi Pradipta

Thanks for your answer

The reason why we use L3 memory instead of mailbox because in some use-cases, the needed data to be transferred from DSS to MSS can reach  about 32k which is for sure exceeding the available size of DSS and MSS mailboxes in chapter 26 in the RTM.

For example, it is needed to transfer the radar detection list from DSS to MSS in order to be sent over CAN and this list might take about 32k.

Would you please tell me in which chapter can I find more details about MPU and L3 memory so I can check with my colleagues and get back to you ?

Hi Pradipta

Thanks for your answer

Please let know if there is any other HW method for the memory consistency between MSS and DSS other than MPU and L3

If there is NO other method, please that's ok for me and the question can be closed