Hi TI Teams,
After we multiplexed the SPI pins into GPIOs when designing the IWR6843AOP, we found that the level could not be flipped and was always in high.
1) Pin multiplexing, which multiplexes SPI pins as normal GPIOs
2) Pin configuration, configured for output mode
3) Pin High-Low Level Flip
So we are wondering is there a limit to pin multiplexing, or is there any mistake with using it this way? Can you help to confirm it?
Thanks,
Kind Regards