Hi,
we have a question concering the maximum SPI clock speed of the PGA970:
On the one hand there is the information (see 6.17 Electrical Characteristics - SPI) which shows a maximum clock speed of 1MHz
and on the other hand you find a SPI timing requirement (see 6.25) which shows the minimum/maximum allowed times for
SCK high/low time = 125ns min., SCK rise/fall time = 7ns max.
=> 125ns +125ns +7ns +7ns = 264ns
=> 3.8MHz approx.
Which information is correct?
Is it allowed to use a SPI clock frequency of e.g. 2.5MHz?
I think this issue should be clarified and the datasheet revised.
Kind regards,
Ferdinand.