AWR6843: MCAN AWR6843 Recieve is not happening If I send from PCAN View software :

/* Standard Id configured in TX application.
 * This macro defined to compare with the received message id in this application */
#define APP_MCAN_STD_ID                          (0xC0U)
#define APP_MCAN_STD_ID_MASK                     (0x7FFU)
#define APP_MCAN_STD_ID_SHIFT                    (18U)
#define APP_MCAN_EXT_ID_MASK                     (0x1FFFFFFFU)


/* Static Function Declarations */
static void    App_mcanIntrISR(void *arg);


void can_test(void *args)
{    
    int32_t                 status = SystemP_SUCCESS;
    HwiP_Params             hwiPrms;
    MCAN_RxBufElement       rxMsg;
    MCAN_ErrCntStatus       errCounter;

    uint32_t                i, bufNum, fifoNum, bitPos = 0U;
    MCAN_RxNewDataStatus    newDataStatus;

    DebugP_log("[MCAN] RX Application, Interrupt mode started ...\r\n");

    /* Enable Interrupts */
    App_mcanEnableIntr();

    /* Transmit And Receive Message */
    for (i = 0U; i < APP_MCAN_MSG_LOOP_COUNT; i++)
    {
        /* Wait for Rx completion */
        SemaphoreP_pend(&gMcanRxDoneSem, SystemP_WAIT_FOREVER);

        /* ClockP_sleep(1); */

        /* Checking for Rx Errors */
        MCAN_getErrCounters(gMcanRxBaseAddr, &errCounter);
        DebugP_assert((0U == errCounter.recErrCnt) &&
                      (0U == errCounter.canErrLogCnt));

        /* Get the new data staus, indicates buffer num which received message */
        MCAN_getNewDataStatus(gMcanRxBaseAddr, &newDataStatus);
        MCAN_clearNewDataStatus(gMcanRxBaseAddr, &newDataStatus);

        /* Select buffer and fifo number, Buffer is used in this app */
        bufNum = 0U;
        fifoNum = MCAN_RX_FIFO_NUM_0;
        
        bitPos = (1U << bufNum);

        if (bitPos == (newDataStatus.statusLow & bitPos))
        {
            MCAN_readMsgRam(gMcanRxBaseAddr, MCAN_MEM_TYPE_BUF, bufNum, fifoNum, &rxMsg);
            /* MCAN_readMsgRam(gMcanRxBaseAddr, MCAN_MEM_TYPE_FIFO, bufNum, (uint32_t)fifoNum, &rxMsg); */
        }
        else
        {
            DebugP_assert(FALSE);
        }

        /* Compare Tx/Rx data */
        App_mcanCompareMsg(&rxMsg);
    }
}

static void App_mcanInitStdFilterElemParams(MCAN_StdMsgIDFilterElement *stdFiltElem,
                                            uint32_t bufNum)
{
    /* sfid1 defines the ID of the standard message to be stored. */
    stdFiltElem->sfid1 = APP_MCAN_STD_ID;
    /* As buffer mode is selected, sfid2 should be bufNum[0 - 63] */
    stdFiltElem->sfid2 = bufNum;
    /* Store message in buffer */
    stdFiltElem->sfec  = MCAN_STD_FILT_ELEM_BUFFER;
    /* Below configuration is ignored if message is stored in buffer */
    stdFiltElem->sft   = MCAN_STD_FILT_TYPE_RANGE;

    return;
}

static void App_mcanEnableIntr(void)
{
    MCAN_enableIntr(gMcanRxBaseAddr, MCAN_INTR_MASK_ALL, (uint32_t)TRUE);
    MCAN_enableIntr(gMcanRxBaseAddr,
                    MCAN_INTR_SRC_RES_ADDR_ACCESS, (uint32_t)FALSE);
    /* Select Interrupt Line 0 */
    MCAN_selectIntrLine(gMcanRxBaseAddr, MCAN_INTR_MASK_ALL, MCAN_INTR_LINE_NUM_0);
    /* Enable Interrupt Line */
    MCAN_enableIntrLine(gMcanRxBaseAddr, MCAN_INTR_LINE_NUM_0, (uint32_t)TRUE);

    /* Take MCAN out of the SW initialization mode */
    MCAN_setOpMode(gMcanRxBaseAddr, MCAN_OPERATION_MODE_NORMAL);
    while (MCAN_OPERATION_MODE_NORMAL != MCAN_getOpMode(gMcanRxBaseAddr))
    {}

    /* Manually Enabling MCAN_CFG Rx related registers */
    SET_MCAN_CFG_RxReg();

    return;
}

static void App_mcanInitMsgRamConfigParams(MCAN_MsgRAMConfigParams
                                           *msgRAMConfigParams)
{
    int32_t status;

    MCAN_initMsgRamConfigParams(msgRAMConfigParams);

    /* Configure the user required msg ram params */
    msgRAMConfigParams->lss = 127U;
    msgRAMConfigParams->lse = 64U;
    msgRAMConfigParams->txBufCnt = 32U;
    msgRAMConfigParams->txFIFOCnt = 0U;
    /* Buffer/FIFO mode is selected */
    msgRAMConfigParams->txBufMode = 0;
    msgRAMConfigParams->txEventFIFOCnt = 0U;
    msgRAMConfigParams->rxFIFO0Cnt = 64U;
    msgRAMConfigParams->rxFIFO1Cnt = 64U;
    /* FIFO blocking mode is selected */
    msgRAMConfigParams->rxFIFO0OpMode = 0U;
    msgRAMConfigParams->rxFIFO1OpMode = 0U;
    msgRAMConfigParams->rxFIFO0WaterMark = 0U;
    msgRAMConfigParams->rxFIFO1WaterMark = 0U;

    status = MCAN_calcMsgRamParamsStartAddr(msgRAMConfigParams);
    DebugP_assert(status == CSL_PASS);

    return;
}


static void App_mcanIntrISR(void *arg)
{
    uint32_t intrStatus;

    intrStatus = MCAN_getIntrStatus(gMcanRxBaseAddr);
    MCAN_clearIntrStatus(gMcanRxBaseAddr, intrStatus);

    /* If FIFO0/FIFO1 is used, then MCAN_INTR_SRC_DEDICATED_RX_BUFF_MSG macro
     * needs to be replaced by MCAN_INTR_SRC_RX_FIFO0_NEW_MSG/
     * MCAN_INTR_SRC_RX_FIFO1_NEW_MSG respectively */

    if (MCAN_INTR_SRC_DEDICATED_RX_BUFF_MSG ==
        (intrStatus & MCAN_INTR_SRC_DEDICATED_RX_BUFF_MSG))
    {
        SemaphoreP_post(&gMcanRxDoneSem);
    }

    if (MCAN_INTR_SRC_TRANS_COMPLETE ==
        (intrStatus & MCAN_INTR_SRC_TRANS_COMPLETE))
    {
        SemaphoreP_post(&gMcanTxDoneSem);
    }

    if (MCAN_INTR_SRC_RX_FIFO0_NEW_MSG ==
            (intrStatus & MCAN_INTR_SRC_RX_FIFO0_NEW_MSG))
    {
        SemaphoreP_post(&gMcanRxDoneSem);
    }

    if (MCAN_INTR_SRC_RX_FIFO1_NEW_MSG ==
            (intrStatus & MCAN_INTR_SRC_RX_FIFO1_NEW_MSG))
    {
        SemaphoreP_post(&gMcanRxDoneSem);
    }

    return;
}