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PGA970: MISO Response

Thevindra Anand
Prodigy 40 points
Part Number: PGA970

Dear TI,

The MISO response for several registers listed below are not coherent with the datasheet;

  • S1_CFG
  • S1_S2_CFG
  • DEMOD2_CONFIG
  • AMUX_CTRL

The datasheet explained that data from desired address under read command is received in 2nd byte of MISO response;

However, for the registers listed above, the obtained data of desired address from read command is received in the 3rd byte:

From the image shown above, read command was sent to read register S1_CFG where it is 0x050300 and the S1 gain selection was 1.67 which means the register should change to 0x050200 after write register command.

However, when read command was sent to see the update of the register after write command, the MISO response was 0x050302 which indicate that the changes was updated to the register but the data change was received in the 3rd byte of the MISO response.

Is the MISO response for the listed register behave consistent for all board of PGA970 as we have tested this issue with several boards of PGA970 at hand?

  • +1
    TI__Guru** 113765 points

    Hi Thevindra Anand,

    I think there may be some confusion as to the addressing.  From the datasheet description in Table 5:

    Note that on reads the register address is always aligned to 16-bit address boundaries.  So you would write to address 0x27, but the read would be 0x26 where the first byte is the S3_ADC_CFG_1 and the address + 1 is the S1_CFG which is byte 3.

    Also note that for each of the registers you mention in your post, the addresses are odd addresses.  So you would need to start at the even address prior and then read from the last byte for the desired data.

    Best regards,

    Bob B